MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 947

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
14–15
16–17
Bits
18
19
20
21
22
23
24
25
EOLNIE End-of-links interrupt enable
EOLSIE End-of-lists interrupt enable
DAHTS Destination address hold transfer size. Indicates the transfer size used for each transaction while
SAHTS Source address hold transfer size. Indicates the transfer size used for each transaction while MR n [SAHE]
EOSIE
Name
DAHE
SAHE
SRW
EIE
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
MR n [DAHE] is set. The byte count register must be in multiples of the size and the destination address
register must be aligned based on the size. The transfer size assigned to MR n [DAHTS] must be equal to or
smaller than that assigned to MR n [BWC] to avoid undefined behavior.
00 1 byte
01 2 bytes
10 4 bytes
11 8 bytes
is set. The byte count register must be in multiples of the size and the source address register must be
aligned based on the size. The transfer size assigned to MR n [SAHTS] must be equal to or smaller than that
assigned to MR n [BWC] to avoid undefined behavior.
00 1 byte
01 2 bytes
10 4 bytes
11 8 bytes
0 Disable destination address hold
1 Enable the DMA controller to hold the destination address of a transfer to the size specified by
0 Disable source address hold
1 Enable the DMA controller to hold the source address of a transfer to the size specified by MR n [SAHTS].
Reserved
0 Normal operation
1 Enable a write to the source address register to simultaneously set MR n [CS], starting a DMA transfer,
0 Do not generate an interrupt at the completion of a data transfer. CLNDAR n [EOSIE] overrides this bit on
1 Generate an interrupt at the completion of a data transfer (That is, SR n [EOSI] is set). This bit overrides
0 Do not generate an interrupt at the completion of a list of DMA transfers.
1 Generate an interrupt at the completion of a list of DMA transfers (That is, NLNDAR n [EOLND] is set).
0 Do not generate an interrupt at the completion of all DMA transfers.
1 Generate an interrupt at the completion of all DMA transfers (That is, NLNDAR n [EOLND] and
Error interrupt enable
0 Do not generate an interrupt if a programming or transfer error is detected.
1 Generate an interrupt if a programming or transfer error is detected.
Destination address hold enable
Source address hold enable
Single register write (Direct mode only; reserved for chaining mode.)
End-of-segments interrupt enable
MR n [DAHTS]. Hardware only supports aligned transfers for this feature.
Hardware only supports aligned transfers for this feature.
when MR n [CDSM/SWSM] is also set. Setting this bit and clearing CDSM/SWSM causes a write to the
destination address register to simultaneously set MR n [CS], starting a DMA transfer.
a link descriptor basis.
the CLNDAR n [EOSIE].
NLSDAR n [EOLSD] are set).
Table 16-5. MR n Field Descriptions (continued)
Description
DMA Controller
16-11