MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 564

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
to reflect the error. If the corresponding bit is not set, then upon detection of an error, the KEU interrupt
status register is updated to reflect the error, causing assertion of the error interrupt signal, and causing the
module to halt processing. The definition of each bit in the KEU interrupt control register is shown in
Figure
Table 12-48
12-86
Address KEU 0x3_E038
Reset
0–48
Bits
49
50
51
52
53
54
55
56
57
58
W
R
12-63.
0
Name
ERE
KSE
DSE
OFE
describes the KEU interrupt control register fields.
ICE
CE
DE
AE
—
—
IE
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
—
Reserved
Integrity check error.
0 ICV check error enabled
1 ICV check error disabled
Reserved
Internal error. An internal processing error was detected while performing encryption.
0 Internal error enabled
1 Internal error disabled
Early read error. A KEU context or IV register was read while the KEU was performing encryption.
0 Early read error enabled
1 Early read error disabled
Context error. A KEU key register, the key size register, data size register, mode register, or IV register
was modified while KEU was performing encryption.
0 Context error enabled
1 Context error disabled
Key size error. An inappropriate value (not 16 or 32 bytes) was written to the KEU key size register
0 Key size error enabled
1 Key size error disabled
Data size error. Indicates that the number of bits to process is out of range.
0 Data size error enabled
1 Data size error disabled
Data error. Indicates that invalid data was written to a register or a reserved mode bit was set.
0 Data error enabled
1 Data error disabled
Address error. An illegal read or write address was detected within the KEU address space.
0 Address error enabled
1 Address error disabled
Output FIFO error. The KEU output FIFO was detected non-empty upon write of KEU data size register
0 Output FIFO non-empty error enabled
1 Output FIFO non-empty error disabled
0
Table 12-48. KEU Interrupt Control Register Field Descriptions
Figure 12-63. KEU Interrupt Control Register
48
ICE
49
0
—
50
0
IE
51
1
ERE CE KSE DSE DE
52
0
53
0
Description
54
0
55
0
56
0
AE OFE IFE
57
0
58
0
59
0
Freescale Semiconductor
—
60
0
Access: Read/Write
IFO OFU —
61
0
62
0
63
0