MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 160

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Reset, Clocking, and Initialization
4.2.1
Table 4-2
Configuration,”
CKSTP_IN and CKSTP_OUT signals are described in
4-2
HRESET_REQ O Hard reset request. Indicates to the board (system in which the MPC8533E is embedded) that a
HRESET
SRESET
READY
Signal
describes some of the system control signals of the MPC8533E.
System Control Signals
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
I/O
O Ready. Multiplexed with TRIG_OUT and QUIESCE. See
describes the signals that also function as reset configuration signals. Note that the
I Hard reset. Causes the MPC8533E to abort all current internal and external transactions and set all
I Soft reset. Causes a machine check interrupt to the e500 core. Note that if the e500 core is not
registers to their default values. HRESET may be asserted completely asynchronously with respect to
all other signals.
condition requiring the assertion of HRESET has been detected.
configured to process machine check interrupts, the assertion of SRESET causes a core checkstop.
SRESET need not be asserted during a hard reset.
Facility,”
Meaning
Meaning
Meaning
Meaning
Table 4-2. System Control Signals—Detailed Signal Descriptions
Timing Assertion/Negation—The MPC8533E Integrated Processor Hardware Specifications gives
Timing Assertion/Negation—May occur any time, synchronous to the core complex bus clock. Once
Timing Assertion—May occur at any time, asynchronous to any clock.
Timing Assertion/Negation—Initial assertion of READY after reset is synchronous with SYSCLK.
State
State
State
State
for more information on TOSR and TRIG_OUT.
Asserted/Negated—See
specific timing information for this signal and the reset configuration signals.
Asserted—A watchdog timer or a boot sequencer failure (see
Negated—Indicates no reset request.
Asserted—Asserting SRESET causes a machine check interrupt (edge sensitive) to the
Negation—Must be asserted for at least two CCB_clk cycles.
Asserted—Indicates that the MPC8533Ehas completed the reset operation and is not in a
Reset Configuration,”
signals during reset.
Sequencer
asserted, HRESET_REQ does not negate until HRESET is asserted.
e500 core. SRESET has no effect while HRESET is asserted. However, the POR
sequence is paused if SRESET is asserted during POR.
power-down state (nap, doze, or sleep) when TOSR[SEL] equals 0b000. See
Section 4.4.2, “Power-On Reset Sequence,”
Subsequent assertion/negation due to power down modes occurs asynchronously.
Mode”) has triggered a request for hard reset.
Chapter 3, “Signal Descriptions,”
for more information on the interpretation of the otherMPC8533E
Chapter 19, “Global Utilities.”
Description
Chapter 21, “Debug Features and Watchpoint
for more information.
Section 4.4.3, “Power-On Reset
and
Section 11.4.5, “Boot
Section 4.4.3, “Power-On
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