MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1187

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

19.5.1.2
CKSTP_IN is not described here because it is not considered a power management signal, although
asserting it does stop the core and a stopped core is technically in a low-power mode. CKSTP_IN is
described in
19.5.1.3
Many blocks in the MPC8533E can dynamically turn off clocks within the block when sections of the
block are idle. This feature is always enabled and occurs automatically.
19.5.1.4
As described in
shut down certain functional blocks within the MPC8533E when they are not needed in a particular
system. DEVDISR can be written by the e500 core or by an external master. Powering down a block in
this way turns off all clocks to that block.
DEVDISR was designed with the expectation that, once initialized by software, it would be modified only
by a hard system reset (HRESET). It is recommended that this register be written only during system
initialization. Blocks disabled by DEVDISR must not be re-enabled without a hard reset. (Setting
DEVDISR[TB] disables the core’s timer facilities, and setting DEVDISR[E500] places the core in the
core_stopped state in which it does not respond to interrupts.) The results of re-enabling previously
disabled blocks (by clearing the corresponding DEVDISR field) without a hard reset are boundedly
undefined.
19.5.1.5
e500 software can place the device in doze, nap, or sleep power-down states by writing to HID0 in the
core. In addition, external masters can write to the memory-mapped POWMGTCR in the MPC8533E to
cause the device to enter doze or sleep modes.
Freescale Semiconductor
Sleep
Mode
Nap
Table 19-29. MPC8533E Power Management Modes—Basic Description (continued)
Section 19.3.2, “Detailed Signal Descriptions.”
Core is stopped with clocks off except to time base
Should flush data cache before entering
Core is stopped with clocks off. Clocks powered down to all
blocks (including core time base) except to the interrupt
controller (PIC) unit
CKSTP_IN is Not Power Management
Dynamic Power Management
Shutting Down Unused Blocks
Software-Controlled Power-Down States
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Functional blocks disabled using DEVDISR cannot respond to
configuration accesses. Any access to configuration, control, and status
registers of a disabled block is a programming error.
Section 19.4.1.12, “Device Disable Register (DEVDISR),”
Description
NOTE
Core Responds To
Snoop
No
No
Interrupts READY ASLEEP
DEVDISR provides a way to
Yes
Yes
Negated Negated
Negated Asserted
Signal States
Global Utilities
19-27