MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 118

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Overview
The interface supports virtual channel 0 (VC0) and traffic class 0 (TC0) only.
Inbound INTx transactions are supported and change the state of one of four level-sensitive interrupts
presented to the PIC. Outbound INTx transactions are not supported.
Message signaled interrupt (MSI) transactions are supported and control up to 256 interrupt sources within
the PIC. Inbound transactions cause specific edge-triggered interrupt sources to be controlled within the
PIC. Outbound MSI transactions are created by software using the MSI Capability Register Sets.
The physical layer of the PCI Express interface operates at a 2.5-Gbaud data rate per lane. The theoretical
unidirectional peak bandwidth is 16 Gbps. Receive and transmit ports operate independently, resulting in
an aggregate theoretical bandwidth of 32 Gbps.
1.3.18
In addition to low-voltage operation and dynamic power management in its execution units, the
MPC8533E supports four power consumption modes: full on, doze, nap, and sleep. The three low-power
modes, doze, nap, and sleep, can be entered under software control in the e500 core or by external masters
accessing a configuration register.
Doze mode suspends execution of instructions in the e500 core. The core is left in a standby mode in which
cache snooping and time base interrupts are still enabled. Device logic external to the processor core is
fully functional in this mode.
Nap mode shuts down clocks to all the e500 functional units except the time base, which can be disabled
separately. No snooping is performed in nap mode, but the device logic external to the processor core is
fully functional.
Sleep mode shuts down not only the e500 core, but also all of the MPC8533E I/O interfaces as well. Only
the interrupt controller and power management logic remain enabled so that the device can be awakened.
1.3.19
The MPC8533E takes in the SYSCLK signal as an input to the platform PLL and multiplies it to generate
the platform clock, which operates at the same frequency as the SDRAM data rate (for example,
666 MHz). The L2 cache also operates at this frequency. The e500 core uses the platform clock as an input
to its PLL, which multiplies it again to generate the core clock.
Although the DDR2 controller clocking is source synchronous, a PLL is used in the local bus memory
controller (LBC) to generate memory clocks. Six differential clock pairs are generated for DDR SDRAMs.
Two clock outputs are generated for the local bus controller (LBC).
1.3.20
The MPC8533E supports a flexible 36-bit physical address map. Conceptually, the address map consists
of local space and external address space. The local address map is 64 Gbytes. The MPC8533E can be
made part of a larger system address space through the mapping of translation windows. This functionality
is included in the address translation and mapping units (ATMUs). Both inbound and outbound translation
1-20
Power Management
Clocking
Address Map
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor