MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 684

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
14-66
22–23
Bits
13
14
15
16
17
18
19
20
21
24
G4T3/WAEN General-purpose line 4 timing 3/wait enable. Bit function is determined by M x MR[GPL4].
G4T1/DLT3
REDO
Name
LOOP
G1T3
G2T1
G2T3
G3T1
G3T3
G5T1
G5T3
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
General-purpose line 1 timing 3. Defines the state (0 or 1) of LGPL1 during bus clock quarter phases
3 and 4 (second half phase)
General-purpose line 2 timing 1. Defines state (0 or 1) of LGPL2 during bus clock quarter phases 1
and 2 (first half phase).
General-purpose line 2 timing 3. Defines the state (0 or 1) of LGPL2 during bus clock quarter phases
3 and 4 (second half phase).
General-purpose line 3 timing 1. Defines the state (0 or 1) of LGPL3 during bus clock quarter phases
1 and 2 (first half phase).
General-purpose line 3 timing 3. Defines the state (0 or 1) of LGPL3 during bus clock quarter phases
3 and 4 (second half phase).
General-purpose line 4 timing 1/delay time 3. The function of this bit is determined by M x MR[GPL4].
If M x MR[GPL4] = 0 and LGPL4/LUPWAIT signal functions as an output (LGPL4), G4T1/DLT3 defines
the state (0 or 1) of LGPL4 during bus clock quarter phases 1 and 2 (first half phase).
If M x MR[GPL4] = 1 and LGPL4/LUPWAIT functions as an input (LUPWAIT), if a read burst or single
read is executed, G4T1/DLT3 defines the sampling of the data bus as follows:
0 In the current word, the data bus should be sampled at the start of bus clock quarter phase 1 of the
1 In the current word, the data bus should be sampled at the start of bus clock quarter phase 3 of the
If M x MR[GPL4] = 0 and LGPL4/LUPWAIT signal functions as an output (LGPL4), G4T3/WAEN
defines the state (0 or 1) of LGPL4 during bus clock quarter phases 3 and 4 (second half phase).
If M x MR[GPL4] = 1 and LGPL4/LUPWAIT functions as an input (LUPWAIT), G4T3/WAEN is used to
enable the wait mechanism:
0 LUPWAIT detection is disabled.
1 LUPWAIT is enabled. If LUPWAIT is detected as being asserted, a freeze in the external signals
General-purpose line 5 timing 1. Defines the state (0 or 1) of LGPL5 during bus clock quarter phases
1 and 2 (first half phase).
General-purpose line 5 timing 3. Defines the state (0 or 1) of LGPL5 during bus clock quarter phases
3 and 4 (second half phase).
Redo current RAM word. Defines the number of times to execute the current RAM word.
00 Once (normal operation)
01 Twice
10 Three times
11 Four times
Loop start/end. The first RAM word in the RAM array where LOOP is 1 is recognized as the loop start
word. The next RAM word where LOOP is 1 is the loop end word. RAM words between, and including
the start and end words, are defined as part of the loop. The number of times the UPM executes this
loop is defined in the corresponding loop fields of the M x MR.
0 The current RAM word is not the loop start word or loop end word.
1 The current RAM word is the start or end of a loop.
next bus clock cycle.
current bus clock cycle.
logical values occurs until LUPWAIT is detected as being negated.
Table 14-28. RAM Word Field Descriptions (continued)
Description
Freescale Semiconductor