MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 667

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

14.4.3.3
The SDRAM machine performs all accesses to SDRAM by using Intel PC133 and JEDEC-standard
SDRAM interface commands. The SDRAM device samples the command and data inputs on the rising
edge of the bus clock. Data at the output of the SDRAM device is sampled on the rising edge of the bus
clock.
The following SDRAM interface commands are provided by setting LSDMR[OP] to a non-zero value
(LSDMR[OP] = 000 sets normal read/write operation):
Freescale Semiconductor
(100: single bank)
AUTO-REFRESH
SELF-REFRESH
(101: all-banks)
(LSDMR[OP])
PRECHARGE
MODE-SET
Command
ACTIVATE
WRITE
READ
(110)
(011)
(111)
(111)
(001)
(010)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
In general (not only during power-on reset) the LSDMR/SDRAM access
ordering protocol should be observed for proper operation.
Intel PC133 and JEDEC-Standard SDRAM Interface Commands
Latches the row address and initiates a memory read of that row. Row data is latched in SDRAM sense
amplifiers and must be restored with a PRECHARGE command before another ACTIVATE is issued.
Allows setting of SDRAM options—CAS latency and burst length. CAS latency depends on the SDRAM
device used. Although some SDRAMs provide burst lengths of 1, 2, 4, 8, or a page, the local bus memory
controller supports only 8-beat bursts for 8-bit and 32-bit port size, or 4-beat bursts for 16-bit port size. The
LBC does not support burst lengths of 1, 2 and a page for SDRAMs. The mode register data (CAS latency
and burst length) is programmed into the LSDMR register by initialization software after reset. After the
LSDMR is set, the LBC transfers the information to the SDRAM device by issuing a MODE-SET command.
Restores data from the sense amplifiers to the appropriate row in the SDRAM device array. Also initializes
the sense amplifiers to prepare for activating another row in the SDRAM device. Note that the LBC uses
LSDA10 to distinguish between PRECHARGE-ALL-BANKS (LSDA10 is high) and
PRECHARGE-SINGLE-BANK (LSDA10 is low). The SDRAMs must be compatible with this format.
Latches the column address and transfers data from the selected sense amplifier on the SDRAM device, to
the output buffer as determined by the column address. During each successive clock, additional data is
driven without additional read commands. At the end of the burst, the page remains open. Burst length is
the one set for this bank. Read data is discarded by the LBC.
Latches the column address and transfers data from the data signals to the selected sense amplifier on the
SDRAM device, as determined by the column address. During each successive clock, additional data is
transferred to the sense amplifiers from the data signals without additional write commands. At the end of
the burst, the page remains open. Burst length is the one set for this bank. LSDDQM[0:3] are inactive and
write data is undefined.
Causes a row to be read in all memory banks (JEDEC SDRAM) as determined by the refresh row address
counter (similar to CBR). The refresh row address counter is internal to the SDRAM device. After being read,
a row is automatically rewritten into the memory array. All banks must be in a precharged state before
executing refresh.
Allows data to be retained in the SDRAM device, even when the rest of the LBC is in a power saving mode
with clocks turned off. When placed in this mode, the SDRAM device is capable of issuing its own refresh
commands, without external clocking from the LBC and the LCKE signal from the LBC is negated. This
command can be issued at any time. Normal operation can be resumed only by setting LSDMR[OP] = 000,
and waiting a minimum of 200 bus cycles before issuing reads or writes to the LBC.
Table 14-26. SDRAM Interface Commands
NOTE
Description
Local Bus Controller
14-49