MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 615

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

13.4.1.2
Each data transfer contains 5–8 bits of data. The ULCR data bit length for the transmitter and receiver
UART devices must agree before a transfer begins; otherwise, a parity or framing error may occur. A
transfer begins when UTHR is written. At that time a START bit is generated followed by 5–8 of the data
bits previously written to the UTHR. The data bits are driven from the least significant to the most
significant bits. After the parity and STOP bits, a new data transfer can begin if new data is written to the
UTHR.
13.4.1.3
The user has the option of using even, odd, no parity, or stick parity (see
Registers (ULCR0, ULCR1).”
attempting to transfer data. When receiving data a parity error can occur if an unexpected parity value is
detected. (See
13.4.1.4
The transmitter device ends the write transfer by generating a STOP bit. The STOP bit is always high. The
user can program the length of the STOP bit(s) in the ULCR. Both the receiver and transmitter STOP bit
length must agree before attempting to transfer data. A framing error can occur if an invalid STOP bit is
detected.
13.4.2
Each UART contains an independent programmable baud-rate generator, that is capable of taking the CCB
clock input and dividing the input by any divisor from 1 to 2
The baud rate is defined as the number of bits per second that can be sent over the UART bus. The formula
for calculating baud rate is as follows:
Therefore, the output frequency of the baud-rate generator is 16 times the baud rate.
The divisor value is determined by the following two 8-bit registers to form a 16-bit binary number:
Upon loading either of the divisor latches, a 16-bit baud-rate counter is loaded.
The divisor latches must be loaded during initialization to ensure proper operation of the baud-rate
generator. Both UART devices on the same bus must be programmed for the same baud-rate before starting
a transfer.
The baud clock can be passed to the performance monitor by enabling the UAFR[BO] bit. This can be used
to determine baud rate errors.
Freescale Semiconductor
•
•
UART divisor most significant byte register (UDMB)
UART divisor least significant byte register (UDLB)
Baud rate = (1/16) × (CCB clock frequency/divisor value)
Baud-Rate Generator Logic
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Section 13.3.1.9, “Line Status Registers (ULSR0,
Data Transfer
Parity Bit
STOP Bit
Both the receiver and transmitter parity definition must agree before
16
– 1.
ULSR1).”)
Section 13.3.1.7, “Line Control
DUART
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