MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 675

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

14.4.3.9
The SDRAM interface supports read and write transactions of between 1 and 8 data beats for transaction
sizes ranging from 1 to 32 bytes. A full burst is performed for each transaction, with the burst length
dependent on the port size. A maximum burst of 8 beats is used for an 8-bit or 32-bit port size, while a
maximum burst of 4 beats is used for a 16-bit port size, as programmed in LSDMR[BL]. For reads that
require less than the full burst length, extraneous data in the burst is ignored and suppressed by the
assertion of LSDDQM[0:3]. For writes that require less than the full burst length, the non-targeted
addresses are protected by driving corresponding LSDDQM bits high (inactive) on the irrelevant cycles of
the burst. However, system performance is not compromised because, if a new transaction is pending, the
SDRAM controller begins executing it immediately, effectively terminating the burst early.
14.4.3.10
The LBC transfers mode register data (CAS latency and burst length) stored in the LSDMR register to the
SDRAM device by issuing the MODE-SET command, as shown in
address carries the mode bits for the command.
14.4.3.11
The memory controller supplies AUTO-REFRESH commands to any connected SDRAM device
according to the interval specified in LSRT (and prescaled by MRTPR[PTP]). This represents the time
period required between refreshes. The values of LSRT and MRTPR depend on the specific SDRAM
devices used and the system clock frequency of the LBC. This value should allow for a potential collision
Freescale Semiconductor
LSDDQM[0:3]
LSDDQM[0:3]
LAD[0:31]
LAD[0:31]
LSDRAS
LSDCAS
LSDRAS
LSDCAS
LSDWE
LSDWE
LCLK
LCS n
LALE
LCLK
LCS n
LALE
TA
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Z
SDRAM Read/Write Transactions
SDRAM MODE-SET Command Timing
SDRAM Refresh
ZZZZZZZZ
1111
COL ADD 1
Figure 14-50. SDRAM Read-After-Write Pipelined, Page Hit
D0
MODE
Figure 14-51. SDRAM MODE-SET Command
D1
1111
MODE-SET
0000
Command
ZZZZZZZZ
D2
D3
COL ADD 2
1111
Z
Figure
0000
14-51. In this case, the latched
D0
D1
Local Bus Controller
D2
1111
D3
14-57
Z