MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 962

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DMA Controller
described by the capability inputs of the DMA controller except for globally coherent transactions that use
the size of the cache coherence granule as described by the mode select input.
The DMA controller supports bandwidth control, which prevents a channel from consuming all the data
bandwidth in the controller. Each channel is allowed to consume the bandwidth of the shared resources as
specified by the bandwidth control value. After the channel uses its allotted bandwidth, the arbiter grants
the next channel access to the shared resources. The arbitration is round robin between the channels. This
feature is also used to implement the external control pause feature. If the external control start and pause
are enabled in the MRn, the channel enters a paused state after transferring the data described in the
bandwidth control. External control can restart the channel from a paused state.
The DMA programming model permits software to program each DMA engine independently to interrupt
on completed segment, chain, or error. It also provides the capability for software to resume the DMA
engine from a hardware halted condition by setting the channel continue bit, MRn[CC]. See
for more complete descriptions of the channel states and state transitions.
16.4.1.1
This mode is primarily included for backward compatibility with existing DMA controllers which use a
simple programming model. This is the default mode out of reset. The different modes of operation under
the basic mode are explained in the following sections.
16.4.1.1.1
In basic direct mode, the DMA controller does not read descriptors from memory, but instead uses the
current parameters programmed in the DMA registers to start the DMA transfer. Software is responsible
for initializing SARn, SATRn, DARn, DATRn, and BCRn registers. The DMA transfer is started when
MRn[CS] is set. Software is expected to program all the appropriate registers before setting MRn[CS] to
a 1. The transfer is finished after all the bytes specified in the byte count register have been transferred or
if an error condition occurs. The sequence of events to start and complete a transfer in basic direct mode
is as follows:
16.4.1.1.2
In basic direct single-write start mode, the DMA controller does not read descriptors from memory, but
instead uses the current parameters programmed in the DMA registers to start the DMA transfer. Software
is responsible for initializing the SATRn, DATRn, and BCRn registers. Setting MRn[SRW] configures the
16-26
1. Poll the channel state (see
2. Initialize SARn, SATRn, DARn, DATRn and BCRn.
3. Set the mode register channel transfer mode bit, MRn[CTM], to indicate direct mode. Other control
4. Clear then set the mode register channel start bit, MRn[CS], to start the DMA transfer.
5. SRn[CB] is set by the DMA controller to indicate the DMA transfer is in progress.
6. SRn[CB] is automatically cleared by the DMA controller after the transfer is finished, or if the
7. End of segment interrupt is generated if MRn[EOSIE] is set.
parameters may also be initialized in the mode register.
transfer is aborted (MRn[CA] transitions from a 0 to 1), or if a transfer error occurs.
Basic Direct Mode
Basic Direct Single-Write Start Mode
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Basic DMA Mode Transfer
Table
16-21), to confirm that the specific DMA channel is idle.
Freescale Semiconductor
Table 16-21