MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 331

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

9.3.2.2
Table 9-4
9.3.2.3
The debug signals MSRCID[0:4] and MDVAL have no function in normal DDR controller operation. A
detailed description of these signals can be found in
9.4
Table 9-5
In this table and in the register figures and field descriptions, the following access definitions apply:
Freescale Semiconductor
Offset
0x000
0x008
0x010
0x018
MCKE[0:3]
MCK[0:5],
MCK[0:5]
•
•
•
•
•
Signal
Reserved fields are always ignored for the purposes of determining access type.
R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
Mixed indicates a combination of access types.
Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
CS0_BNDS—Chip select 0 memory bounds
CS1_BNDS—Chip select 1 memory bounds
CS2_BNDS—Chip select 2 memory bounds
CS3_BNDS—Chip select 3 memory bounds
Memory Map/Register Definition
contains the detailed descriptions of the clock signals of the DDR controller.
shows the register memory map for the DDR memory controller.
Clock Interface Signals
Debug Signals
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
I/O
O
O
DRAM clock outputs and their complements. See
Clock enable. Output signals used as the clock enables to the SDRAM. MCKE[0:3] can be negated to stop
clocking the DDR SDRAM.
Meaning
Meaning
Timing Assertion/Negation—Timing is controlled by the DDR_CLK_CNTL register at offset 0x130.
Timing Assertion/Negation—Asserted when DDR_SDRAM_CFG[MEM_EN] is set. Can be negated
State
State
Table 9-4. Clock Signals—Detailed Signal Descriptions
Asserted—Clocking to the SDRAM is enabled.
Negated—Clocking to the SDRAM is disabled and the SDRAM should ignore signal transitions
Asserted/Negated—The JEDEC DDR SDRAM specifications require true and complement
High impedance—Always driven.
Table 9-5. DDR Memory Controller Memory Map
clocks. A clock edge is seen by the SDRAM when the true and complement cross.
on MCK or MCK. MCK/MCK are don’t cares while MCKE[0:3] are negated.
when entering dynamic power management or self refresh. Will be asserted again when
exiting dynamic power management or self refresh.
Register
Section 21.4.2, “DDR SDRAM Interface
Description
Section 9.5.4.1, “Clock Distribution.”
Access
R/W
R/W
R/W
R/W
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
DDR Memory Controller
Section/Page
9.4.1.1/9-11
9.4.1.1/9-11
9.4.1.1/9-11
9.4.1.1/9-11
Debug.
9-9