MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 685

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

14.4.4.4.2
If BRn[MSEL] of the accessed bank selects a UPM on the currently requested cycle, the UPM manipulates
the LCSn for that bank with timing as specified in the UPM RAM word CSTn fields. The selected UPM
affects only the assertion and negation of the appropriate LCSn signal. The state of the selected LCSn
Freescale Semiconductor
26–27
Bits
25
28
29
30
31
Name
EXEN
TODT
LAST
AMX
UTA
NA
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Chip-Select Signal Timing (CST n )
Exception enable. Allows branching to an exception pattern at the exception start address (EXS).
When an internal bus monitor time-out exception is recognized and EXEN in the RAM word is set, the
UPM branches to the special exception start address (EXS) and begins operating as the pattern
defined there specifies.
The user should provide an exception pattern to negate signals controlled by the UPM in a controlled
fashion. For DRAM control, a handler should negate RAS and CAS to prevent data corruption. If EXEN
= 0, exceptions are ignored by UPM (but not by Local Bus) and execution continues. After the UPM
branches to the exception start address, it continues reading until the LAST bit is set in the RAM word.
0 The UPM continues executing the remaining RAM words, ignoring any internal bus monitor
1 The current RAM word allows a branch to the exception pattern after the current cycle if an
Address multiplexing. Determines the source of LAD[0:31] during a LALE phase. Any change in the
AMX field initiates a new LALE (address) phase.
00 LAD[0:31] is the non-multiplexed address. For example, column address.
01 Reserved
10 LAD[0:31] is the address multiplexed according to M x MR[AM]. For example, row address.
11 LAD[0:31] is the contents of MAR. Used, for example, to initialize a mode.
Note that Source ID debug mode is only supported for the AMX = 00 setting.
Next burst address. Determines when the address is incremented during a burst access.
0 The address increment function is disabled.
1 The address is incremented in the next cycle. In conjunction with the BR n [PS], the increment value
UPM transfer acknowledge. Indicates assertion of transfer acknowledge in the current cycle.
0 Transfer acknowledge is not asserted in the current cycle.
1 Transfer acknowledge is asserted in the current cycle.
Turn-on disable timer. The disable timer associated with each UPM allows a minimum time to be
guaranteed between two successive accesses to the same memory bank. This feature is critical when
DRAM requires a RAS precharge time. TODT turns the timer on to prevent another UPM access to
the same bank until the timer expires.The disable timer period is determined in M x MR[DS n ]. The
disable timer does not affect memory accesses to different banks. Note that TODT must be set
together with LAST, otherwise it is ignored.
0 The disable timer is turned off.
1 The disable timer for the current bank is activated preventing a new access to the same bank (when
Last word. When LAST is read in a RAM word, the current UPM pattern terminates and control signal
timing set in the RAM word is applied to the current (and last) cycle. However, if the disable timer is
activated and the next access is to the same bank, execution of the next UPM pattern is held off and
the control signal values specified in the last word are extended in duration for the number of clock
cycles specified in M x MR[DS n ].
0 The UPM continues executing RAM words.
1 Indicates the last RAM word in the program. The service to the UPM request is done after this cycle
time-out.
exception condition is detected.
of the state of LA[27:31] is 1, 2 or 4 for port sizes of 8-bits, 16-bits and 32-bits, respectively.
controlled by the UPMs) until the disable timer expires. For example, precharge time.
concludes.
Table 14-28. RAM Word Field Descriptions (continued)
Description
Local Bus Controller
14-67