MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 112

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Overview
Line locks can be set in a variety of ways. The Book E architecture defines instructions that explicitly set
and clear locks in the L2. These instructions are supported by the core complex and the L2 controller. In
addition, the L2 controller can be configured to lock all lines that fall into either of two specified address
ranges when the line is allocated. Finally, the entire cache can be locked by writing to a configuration
register in the L2 cache controller.
The status array tracks line locks as either instruction locks or data locks for each line, and the status array
supports flash clearing of all instruction locks or data locks separately by writes to configuration registers
in the L2 controller.
1.3.5
The e500 coherency module (ECM) provides a mechanism for I/O-initiated transactions to snoop the bus
between the e500 core and the integrated L2 cache in order to maintain coherency across local cacheable
memory. It also provides a flexible switch-type structure for core- and I/O-initiated transactions to be
routed or dispatched to target modules on the device.
1.3.6
The MPC8533E supports DDR and DDR2 SDRAM. The memory interface controls main memory
accesses and provides for a maximum of 16 Gbytes of main memory. The memory controller can be
configured to support the various memory sizes through software initialization of on-chip configuration
registers.
The MPC8533Esupports a variety of SDRAM configurations. SDRAM banks can be built using DIMMs
or directly-attached memory devices. Sixteen multiplexed address signals provide for device densities of
64 Mbits, 128 Mbits, 256 Mbits, 512 Mbits, 1 Gbits, 2 Gbits and 4 Gbits. Four chip select signals support
up to four banks of memory. The MPC8533E supports bank sizes from 64 Mbytes to 4 Gbytes. Nine
column address strobes (MDM[0:8]) are used to provide byte selection for memory bank writes.
The MPC8533E can be configured to retain the currently active SDRAM page for pipelined burst accesses.
Page mode support of up to 16 simultaneously open pages (32 for DDR2) can dramatically reduce access
latencies for page hits. Depending on the memory system design and timing parameters, using page mode
can save 3 to 4 clock cycles from subsequent burst accesses that hit in an active page.
The MPC8533E supports error checking and correction (ECC) for system memory. Using ECC, the
MPC8533E detects and corrects all single-bit errors and detects all double-bit errors and all errors within
a nibble.
The MPC8533E can invoke a level of system power management by asserting the MCKE SDRAM signal
on-the-fly to put the memory into a low-power sleep mode.
The MPC8533E offers the following options to support battery-backed main memory:
1-14
•
Hardware based
An external voltage sense device is connected to the MPC8533E via an interrupt line. The external
interrupt from this device is steered through the MPC8533E interrupt controller to the IRQ_OUT
signal. The IRQ_OUT signal from the interrupt controller is steered to an enable bit in the DDR
controller which immediately causes main memory to enter self-refresh mode.
e500 Coherency Module (ECM)
DDR SDRAM Controller
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor