MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1025

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

17.4.2.3
PCI defines three physical address spaces—PCI memory space, PCI I/O space, and PCI configuration
space. Access to the PCI memory and I/O space is straightforward, although one must take into account
the local memory access window and address translation being used. The address translation registers are
described in
described in
Address decoding on the PCI bus is performed by every device for every PCI transaction. Each agent is
responsible for decoding its own address. PCI supports two types of address decoding—positive decoding
and subtractive decoding. For positive decoding, each device looks for accesses in the address range that
the device has been assigned. For subtractive decoding, one device on the bus looks for accesses that no
other device has claimed. See
transactions.
The information contained in the two low-order address bits (PCI_AD[1:0]) varies by the address space
(memory, I/O, or configuration). Regardless of the encoding scheme, the two low-order address bits are
always included in parity calculations.
17.4.2.3.1
For memory accesses, PCI defines two types of burst ordering controlled by the two low-order bits of the
address—linear incrementing (PCI_AD[1:0] = 0b00) and cache wrap mode (PCI_AD[1:0] = 0b10), as
shown in
initiator, the PCI controller always encodes PCI_AD[1:0] = 00 for PCI memory space accesses. As a
target, the PCI controller executes a target disconnect after the first data phase completes if
Freescale Semiconductor
1
BE[3:0]
PCI_C/
1010
1011
1100
1101
1110
1111
Reserved command encodings are reserved for future use. The PCI controller does not respond to these commands.
Configuration-
read
Configuration-
write
Memory-read-
multiple
Dual-address-
cycle
Memory-read-
line
Memory-write-
and-invalidate
Table
Command
PCI Bus
Section 17.3.1, “PCI Memory-Mapped Registers.”
Section 17.4.2.11, “Configuration Cycles.”
Addressing
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Memory Space Addressing
17-48. The other two PCI_AD[1:0] possibilities (0b01 and 0b11) are reserved. As an
Supported
Initiator
as an
Yes
Yes
Yes
Yes
Yes
No
Section 17.4.2.4, “Device Selection,”
Table 17-47. PCI Bus Commands (continued)
Agent mode
Agent mode
as a Target
Supported
only
only
Yes
Yes
Yes
Yes
Accesses the 256-byte configuration space of a PCI agent. A specific
agent is selected when its IDSEL signal is asserted during the address
phase. See
Similar to the memory-read command, but also causes a prefetch of the
next cache line (32 bytes).
Used to transfer a 64-bit address (in two 32-bit address cycles) to 64-bit
addressable devices.
Indicates that an initiator is requesting the transfer of an entire cache
line. This occurs only when the processor is performing a burst read.
Note that these processors perform burst reads only when the
appropriate cache is enabled and the transaction is not cache-inhibited.
Indicates that an initiator is transferring an entire cache line; if this data
is in any cacheable memory, that cache line needs to be invalidated.
Section 17.4.2.11, “Configuration Cycles,”
Access to the PCI configuration space is
for information about claiming
Definition
for details.
PCI Bus Interface
17-47