MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 507

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Offset PKEU 0x3_C028
12.4.1.5
This register, shown in
Table 12-11
12.4.1.6
This status register contains 6 fields that reflect the state of PKEU internal fields.
The PKEU status register is read-only. Writing to this location results in an address error being reflected
in the PKEU interrupt status register.
The PKEU status register is shown in
Reset
Freescale Semiconductor
Offset PKEU 0x3_C018
0–60
Reset
Bits Name
61
62
63
W
R
W
R
0
0
SR
MI
—
RI
describes the PKEU reset control register fields.
Reserved
Reset interrupt. Writing this bit active high causes PKEU interrupts signaling DONE and ERROR to be reset. It
further resets the state of the PKEU interrupt status register.
0 Don’t reset
1 Reset interrupt logic
Module initialization. Module initialization is nearly the same as software reset, except that the interrupt control
register remains unchanged. This module initialization includes execution of an initialization routine, completion
of which is indicated by the RESET_DONE bit in the PKEU status register
Register
0 Don’t reset
1 Reset most of PKEU
SW reset. Software reset is functionally equivalent to hardware reset (the RESET signal), but only for the PKEU.
All registers and internal state are returned to their defined reset state. Upon negation of SW_RESET, the PKEU
enters a routine to perform proper initialization of the parameter memories. The RESET_DONE bit in the PKEU
status register indicates when this initialization routine is complete
(PKEUSR)”).
0 Don’t reset
1 Full PKEU reset
PKEU Reset Control Register (PKEURCR)
PKEU Status Register (PKEUSR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
(PKEUSR)”).
Table 12-11. PKEU Reset Control Register Field Descriptions
Figure
12-11, contains three reset options specific to the PKEU.
Figure 12-11. PKEU Reset Control Register
Figure 12-12. PKEU Status Register
Figure 12-12
—
—
All zeros
All zeros
Description
(Section 12.4.1.6, “PKEU Status Register
(Section 12.4.1.6, “PKEU Status
56 57
Z HALT
Security Engine (SEC) 2.1
58
Access: Read/Write
59 60 61 62 63
—
60 61 62 63
Access: Read
RI MI SR
IE ID RD
12-29