MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 758

Manufacturer Part Number

MPC8533EVTAQGA

MPU POWERQUICC 783-PBGA

Manufacturer

Freescale Semiconductor

Processor Type

MPC85xx PowerQUICC III 32-Bit

0.95 V ~ 1.05 V

Mounting Type

Surface Mount

Package / Case

783-BBGA, FCBGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Manufacturer

BOSTOCK HK LIMITED

Part Number:

MPC8533EVTAQGA

Manufacturer:

Freescale Semiconductor

Enhanced Three-Speed Ethernet Controllers

The interrupt mask register provides control over which possible interrupt events in the IEVENT register

are permitted to participate in generating hardware interrupts to the PIC. All implemented bits in this

IMASK registers are set, the PIC will receive an interrupt (for each eTSEC these are grouped into transmit,

receive, and error/diagnostic interrupts). The interrupt signal remains asserted until either the IEVENT bit

is cleared, by writing a 1 to it, or by writing a 0 to the corresponding IMASK bit.

Offset eTSEC1:0x2_4014; eTSEC3:0x2_6014

describes the fields of the IMASK register.

describes the IMASK register.

MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Interrupt Mask Register (IMASK)

Babbling receiver interrupt enable

Receive control interrupt enable

Busy interrupt enable

Ethernet controller bus error enable

MIB counter overflow interrupt enable

Graceful transmit stop complete interrupt enable

Figure 15-5. IMASK Register Definition

Table 15-8. IMASK Field Descriptions

Freescale Semiconductor

Access: Read/Write