MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 792

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
reside in a different memory region (based at RBASEH).
RBDBPH register.
Table 15-35
15.5.3.3.11 Receive Buffer Descriptor Pointers 0–7 (RBPTR0–RBPTR7)
RBPTR0–RBPTR7 each contains the low-order 32 bits of the next receive buffer descriptor address for
their respective RxBD ring.
value of their ring’s associated RBASE when the RBASE register is written by software. Software must
not write RBPTRn while eTSEC is actively receiving frames. However, RBPTRn can be modified when
the receiver is disabled or when no Rx buffer is in use (after a GRACEFUL STOP RECEIVE command is
issued and the frame completes its reception) in order to change the next RxBD eTSEC receives.
Table 15-23
15-62
28–31
29–31
0–27
0–28
Bits
Bits
Offset eTSEC1:0x2_4384+8× n ; eTSEC3:0x2_6384+8× n ×
Offset eTSEC1:0x2_4380; eTSEC3:0x2_6380
Reset
Reset
W
W
R
R
RBDBPH Most significant bits common to all data buffer addresses contained in RxBDs. The user must initialize
RBPTR n
0
0
Name
Name
—
—
describes the fields of the RBDBPH register.
describes the fields of the RBPTRn register.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
RBDBPH before enabling the eTSEC receive function.
Current RxBD pointer for RxBD ring n . Points to the current BD being processed or to the next BD the
receiver uses when it is idling. After reset or when the end of the RxBD ring is reached,
eTSEC initializes RBPTR n to the value in the corresponding RBASE n . The RBPTR register is internally
written by the eTSEC’s DMA controller during reception. The pointer increments by 8 (bytes) each time a
descriptor is closed successfully by the eTSEC. Note that the 3 least-significant bits of this register are
read only and zero.
Reserved
Figure 15-33. RBPTR0–RBPTR7 Register Definition
Figure 15-33
Figure 15-32. RBDBPH Register Definition
Table 15-35. RBDBPH Field Descriptions
Table 15-36. RBPTR n Field Descriptions
describes the RBPTR registers. These registers takes on the
RBPTR n
—
All zeros
All zeros
Description
Description
Figure 15-32
describes the definition for the
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
27 28
28 29
RBDBPH
—
31
31