MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 366

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DDR Memory Controller
Section 9.5.12, “Error Management,”
9-44
1. All signals are connected in common (in parallel) except for MCS[0:3], MCK[0:5], MDM[0:8], and the data bus signals.
2. Each of the MCS[0:3] signals correspond with a separate physical bank of memory.
3. Buffering may be needed if large memory arrays are used.
4. MCK[0:5] may be apportioned among all memory devices. Complementary bus is not shown.
DDR
Controller
MDQS[0:8]
MDQ[0:63]
MECC[0:7]
MDM[0:8]
MCK[0:5]
MCK[0:5]
MBA[2:0]
MCS[0:3]
MA[15:0]
MRAS
MCAS
MCKE
MWE
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure 9-36. Example 256-Mbyte DDR SDRAM Configuration With ECC
MCS0
0
1
2
3
4
5
6
7
8
A[11:0]
BA[1:0]
RAS
CAS
WE
CKE
CK
CS
DM
A[11:0]
BA[1:0]
RAS
CAS
WE
CKE
CK
CS
DM
8M × 8 SDRAM
8M × 8 SDRAM
A[0-11]
BA[0-1]
RAS
CAS
CKE
CLK
CS
DM
A(11-0)
BA(1-0)
RAS
CAS
CKE
CLK
CS
DM
2Mx8 SDRAM
A(11-0)
BA(1-0)
RAS
CAS
CKE
CLK
CS
DM
2Mx8 SDRAM
A[0-11]
BA[0-1]
RAS
CAS
CKE
CLK
CS
DM
2 Mx8 SDRAM
A[0-11]
BA[0-1]
RAS
CAS
CKE
CLK
CS
DM
2Mx8 SDRAM
A[0-11]
BA[0-1]
RAS
CAS
CKE
CLK
CS
DM
2Mx8 SDRAM
A[0-11]
BA[0-1]
RAS
CAS
CKE
CLK
CS
DM
2Mx8 SDRAM
2 Mx8 SDRAM
DQ[0-7]
DQ[7:0]
DQ[7:0]
Bank 0
8M × 72 (64 Mbytes)
MDQS
DQ(7-0)
MDQS
DQ(7-0)
DQ[0-7]
DQ[0-7]
To all SDRAM
Devices in
Common
DQ[0-7]
explains how the DDR memory controller handles errors.
DQ[0-7]
Memory Data Bus and Strobes
MDQS[8]
MDQS[0]
MDQ[0:7]
MDQ[8:15]
MDQ[16:23]
MDQ[24:31]
MDQ[32:39]
MDQ[40:47]
MDQ[48:55]
MDQ[56:63]
ECC[0:7]
MDQS[7]
MCS1
0
1
2
3
4
5
6
7
8
A[11:0]
BA[1:0]
RAS
CAS
WE
CKE
CK
CS
DM
A[11:0]
BA[1:0]
RAS
CAS
CKE
CK
CS
DM
WE
8M × 8 SDRAM
8M × 8 SDRAM
A[0-11]
BA[0-1]
RAS
CAS
CKE
CLK
CS
DM
A(11-0)
BA(1-0)
RAS
CAS
CKE
CLK
CS
DM
2Mx8 SDRAM
A(11-0)
BA(1-0)
RAS
CAS
CKE
CLK
CS
DM
2 Mx8 SDRAM
A[0-11]
BA[0-1]
RAS
CAS
CKE
CLK
CS
DM
2Mx8 SDRAM
A[0-11]
BA[0-1]
RAS
CAS
CKE
CLK
CS
DM
2Mx8 SDRAM
A[0-11]
BA[0-1]
RAS
CAS
CKE
CLK
CS
DM
2Mx8 SDRAM
Bank 1
8M × 72 (64 Mbytes)
A[0-11]
BA[0-1]
RAS
CAS
CKE
CLK
CS
DM
2 Mx8 SDRAM
2Mx8 SDRAM
DQ[0-7]
DQ[7:0]
DQ[7:0]
DQ(7-0)
MDQS
MDQS
DQ(7-0)
DQ[0-7]
DQ[0-7]
DQ[0-7]
DQ[0-7]
Freescale Semiconductor
MDQS[8]
MDQS[0]
MDQ[0:7]
MDQ[8:15]
MDQ[16:23]
MDQ[24:31]
MDQ[32:39]
MDQ[40:47]
MDQ[48:55]
MDQ[56:31]
ECC[0:7]
MDQS[7]
Banks 2–3