MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 524

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
Table 12-23
12.4.3.7
The interrupt status register, shown in
not masked, via the AFEU interrupt control register.
12-46
Address AFEU 0x3_8030
40–47
48–55
56–57
59–60
0–39
Bits
Reset
58
61
62
63
W
R
Name
HALT Halt. Indicates that the AFEU has halted due to an error.
OFL
0
IFL
RD
—
—
—
IE
ID
describes the AFEU status register fields.
AFEU Interrupt Status Register (AFEUISR)
Reserved
The number of dwords currently in the output FIFO
The number of dwords currently in the input FIFO
Reserved
0 AFEU not halted
1 AFEU halted
Note: Because the error causing the AFEU to stop operating may be masked before reaching the interrupt
Reserved
Interrupt error. This status bit reflects the state of the ERROR interrupt signal, as sampled by the controller
interrupt status register
0 AFEU is not signaling error
1 AFEU is signaling error
Interrupt done. This status bit reflects the state of the DONE interrupt signal, as sampled by the controller
interrupt status register
0 AFEU is not signaling done
1 AFEU is signaling done
Reset done. This status bit, when high, indicates that AFEU has completed its reset sequence, as reflected in
the signal sampled by the appropriate channel.
0 Reset in progress
1 Reset done
Note: Reset done resets to 0, but has typically switched to 1 by the time a user checks the register, indicating
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
status register, the AFEU interrupt status register is used to provide a second source of information
regarding errors preventing normal operation.
the EU is ready for operation.
Table 12-23. AFEU Status Register Field Descriptions
—
Figure 12-26. AFEU Interrupt Status Register
(Section 12.6.5.3, “Interrupt Status Register
(Section 12.6.5.3, “Interrupt Status Register
Figure
12-26, tracks the state of possible errors, if those errors are
50 51
IE ERE CE KSE DSE ME AE OFE IFE — IFO OFU —
All zeros
Description
52
53
54
55
(ISR)”).
(ISR)”).
56
57
58
Freescale Semiconductor
59
Access: Read-only
60
61
62
63