MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1037

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

layout shown in
header specific to the PCI controller is described in
Table 17-49
provided in the PCI Local Bus Specification, Rev. 2.2.
Freescale Semiconductor
Offset (Hex)
0x10–0x27
Address
0x0C
0x0D
0x0E
0x00
0x02
0x04
0x06
0x08
0x09
0x0F
Max_Lat
BIST
summarizes the configuration header registers. Detailed descriptions of these registers are
Base address registers
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure
Register Name
Cache line size
Latency timer
Header type
Revision ID
Class code
Command
Vendor ID
Device ID
Status
Subsystem ID
BIST
Device ID
17-58. The rest of the 256-byte configuration space is device-specific. The PCI
Status
Table 17-49. PCI Configuration Space Header Summary
Figure 17-58. Standard PCI Configuration Header
Header Type
Class Code
Identifies the manufacturer of the device (assigned by the PCI SIG (special-interest
group) to ensure uniqueness).
Identifies the particular device (assigned by the vendor).
Provides coarse control over a device’s ability to generate and respond to PCI bus
cycles
Records status information for PCI bus-related events
Specifies a device-specific revision code (assigned by vendor)
Identifies the generic function of the device and (in some cases) a specific
register-level programming interface
Specifies the system cache line size in 32-bit units
Specifies the value of the latency timer in PCI bus clock units for the device when
acting as an initiator
Bits 0–6 identify the layout of bytes 0x10–0x3F; bit 7 indicates a multifunction device.
The most common header type (0x00) is shown in
Optional register for control and status of built-in self test (BIST)
Address mapping information for memory and I/O space
Min_Gnt
Expansion ROM Base Address
Base Address Registers
Reserved
Reserved
Reserved
Section 17.3.2, “PCI Configuration Header.”
Latency Timer
Interrupt Pin
Description
Subsystem Vendor ID
Command
Vendor ID
Figure 17-58
Cache Line Size
Interrupt Line
Revision ID
Address Offset (Hex)
and in this table.
PCI Bus Interface
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
17-59