MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 653

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Figure 14-22
and that for the duration of LALE, LCSn (or any other control signal) remains negated or frozen.
14.4.1.4
The memory controller provides a data buffer control signal for the local bus (LBCTL). This signal is
activated when a GPCM or UPM controlled bank is accessed. LBCTL can be disabled by setting
ORn[BCTLD]. Access to an SDRAM machine controlled bank does not activate the LBCTL control.
LBCTL can be further configured by LBCR[BCTLC] to act as an extra LWE or an extra LOE signal when
in GPCM mode.
If LBCTL is configured as a data buffer control (LBCR[BCTLC] = 00), the signal is asserted (high) on the
rising edge of the bus clock on the first cycle of the memory controller operation, coincident with LALE. If
the access is a write, LBCTL remains high for the whole duration. However, if the access is a read, LBCTL
is negated (low) with the negation of LALE so that the memory device is able to drive the bus. If
back-to-back read accesses are pending, LBCTL is asserted (high) one bus clock cycle before the next
transaction starts (that is, one bus clock cycle before LALE) to allow a whole bus cycle for the bus to turn
around before the next address is driven.
If an external bus transceiver is used, LBCTL should be used to signify the write direction when high. Note
that the default (reset and bus idle) value of LBCTL is also high.
14.4.1.5
The LBC supports the following kinds of atomic bus operations (set by BRn[ATOM]):
Freescale Semiconductor
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Read-after-write atomic (RAWA). When a write access hits a memory bank in which ATOM = 01,
the LBC reserves the selected memory bank for the exclusive use of the accessing master.
While the bank is reserved, no other device can be granted access to this bank. The reservation is
released when the master that created it accesses the same bank with a read transaction. Additional
write transactions prior to the releasing read do not change reservation status, but are otherwise
processed normally. If the master fails to release the reservation within 256 bus clock cycles, the
reservation is released and an atomic error is reported (if enabled). This feature is intended for
CAM operations.
Write-after-read atomic (WARA). When a read access hit a memory bank in which ATOM = 10,
the LBC reserves the bus for the exclusive use of the accessing master.
shows LALE, TA (internal), and LCSn. Note that TA and LALE are never asserted together,
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Data Buffer Control (LBCTL)
Atomic Operation
Figure 14-22. Basic LBC Bus Cycle with LALE, TA, and LCS n
LCLK
LALE
LCS n
LAD
TA
Address
Data
Local Bus Controller
14-35