MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 439

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

10.3.7.5
The messaging interrupt vector/priority registers (MIVPRs), shown in
and format as the GTVPRs, except they apply to messaging interrupts.
Table 10-44
10.3.7.6
The messaging interrupt destination registers (MIDRs), shown in
the messaging interrupts. MIDR enables the user to direct the interrupt to either the external interrupt
output pin (IRQ_OUT), the core’s critical interrupt input (cint), or to its normal interrupt input (int).
Freescale Semiconductor
2–30
12–15 PRIORITY Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A priority level
16–31 VECTOR Vector. The vector value in this field is returned when the interrupt acknowledge (IACK) register is read and
Bits Name
2–11
31
Bits
Offset MIVPR0: 0x5_1600, MIVPR1: 0x5_1620, MIVPR2: 0x5_1640, MIVPR3: 0x5_1660
Reset
0
1
W
R
P0
—
MSK
Name
MSK
1
0
—
A
Reserved
Processor 0. Indicates that processor 0 handles any interrupt. This bit is meaningful only in a multi-core device.
For a single-core device, interrupts serviced internally are directed to processor 0. Permanently set and read only.
1 Interrupt directed to processor 0.
describes the MIVPR fields.
A
0
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
1
Messaging Interrupt Vector/Priority Registers (MIVPR0–MIVPR3)
Messaging Interrupt Destination Registers (MIDR0–MIDR3)
Mask. Mask interrupts from this source.
0 An interrupt request is generated when the corresponding IPR field is set.
1 Further interrupts from this source are disabled.
Activity. Indicates an interrupt has been requested or is in-service. Note this field is read only. The VECTOR
and PRIORITY values should not be changed while MIVPR n [A] is set.
0 No current interrupt activity associated with this source.
1 The interrupt field for this source is set in the IPR or ISR.
Reserved
of 0 disables interrupts from this source.
this interrupt resides in the interrupt request register (IRR) shown in
0
2
Figure 10-40. Messaging Interrupt Vector/Priority Registers (MIVPRs)
0 0
Table 10-43. IIDR n Field Descriptions (continued)
0
—
0 0 0 0 0 0 0 0 0 0 0
Table 10-44. MIVPR n Field Descriptions
11 12
PRIORITY
Description
Description
15 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure
Figure
10-41, control the destination for
Figure
10-40, have the same fields
Programmable Interrupt Controller
VECTOR
10-48.
Access: Mixed
10-43
31