MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1061

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

18.3.3
18.3.3.1
The PCI Express PME and message detect register, shown in
PME events that are detected by the PCI Express controller. This register is a write-1-to-clear type register.
The fields of the PCI Express PME and message detect register are described in
Freescale Semiconductor
Offset 0x020
Reset
23–24
0–15
Bits
16
17
18
19
20
21
22
W
R
0
ENL23 Entered L2/L3 ready state. This bit indicates that the PCI Express controller has entered L2/L3 state. This is
EXL23 Exit L2/L3 ready state. This bit indicates that the PCI Express controller has exited the L2/L3 state. This is
Name
PTAT
HRD
PTO
LDD
—
—
—
PCI Express Power Management Event and Message Registers
Figure 18-7. PCI Express PME and Message Detect Register (PEX_PME_MES_DR)
PCI Express PME and Message Detect Register (PEX_PME_MES_DR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
PME turn off. This bit indicates the detection of a PME_Turn_Off message. This bit is only valid in EP mode.
1 A PME_Turn_Off_message is detected
0 No PME_Turn_Off message detected
PME to ack time-out. This bit indicates the detection of a PME_to_ack time-out condition.
This bit is only valid in RC mode.
1 A PME_TO_Ack time-out condition is detected
0 No PME_TO_Ack time-out condition detected
only valid in RC mode.
1 L2/L3 ready state has been entered
0 L2/L3 ready state has not been entered
only valid in RC mode.
1 Exit L2/L3 state has been detected
0 Exit L2/L3 state not detected
Reserved. Note that during normal operation, this bit may be set (falsely). The bit may be ignored and
cleared (w1c) without consequence.
Hot reset detected. This bit indicates that the PCI Express controller has detected a hot reset condition on
the link. The controller will be reset and will clean up all outstanding transactions. Link retraining will take
place once hot reset state is exited. This is valid only in EP mode.
1 Hot reset request has been detected
0 Hot reset request not detected
Link down detected. This bit indicates that a link down condition has been detected. The controller will be
reset and then will clean up all outstanding transactions. Link retraining will take place once the controller
has cleaned itself up.
1 Link down has been detected
0 Link down not detected
Reserved
—
Table 18-9. PEX_PME_MES_DR Field Descriptions
15
PTO PTAT ENL23 EXL23
w1c w1c
16
17
w1c
18
w1c
19
All zeros
Description
—
20
HRD LDD
w1c w1c
21
Figure
22
23 24
18-7, logs inbound messages and
—
AION AIB AIOF PION PIB PIOF ABP
w1c w1c w1c w1c w1c w1c w1c
25
26
PCI Express Interface Controller
Table
27
18-9.
28
29
Access: w1c
30
18-13
31