MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 680

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
Note that transfer acknowledges (UTA bit in the RAM word) are ignored for software (RUN command)
requests, and hence the LAD signals remain high-impedance unless the normal initial LALE occurs or the
RUN pattern causes assertion of LALE to occur on changes to the RAM word AMX field.
14.4.4.1.4
When the LBC under UPM control initiates an access to a memory device and an exception occurs (bus
monitor time-out), the UPM provides a mechanism by which memory control signals can meet the device’s
timing requirements without losing data. The mechanism is the exception pattern that defines how the
UPM negates its signals in a controlled manner.
14.4.4.2
The UPM is a micro sequencer that requires microinstructions or RAM words to generate signal timings
for different memory cycles. Follow these steps to program UPMs:
Patterns are written to the RAM array by setting MxMR[OP] = 01 and accessing the UPM with any write
transaction that hits the relevant chip select. The entire array is thus programmed by an alternating series
of writes: to MDR (RAM word to be written) each time followed by a read from MDR and then followed
by a (dummy) write transaction to the relevant UPM assigned bank. A read from MDR is required to
ensure that the MDR update has occurred prior to the (dummy) write transaction.
RAM array contents may also be read for debug purposes, for example, by alternating dummy read
transactions, each time followed by reads of MDR (when MxMR[OP] = 10).
14-62
1. Set up BRn and ORn registers.
2. Write patterns into the RAM array.
3. Program MRTPR, LURT and MAMR[RFEN] if refresh is required.
4. Program MxMR.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Programming the UPMs
MxMR/MDR registers should not be updated while dummy read/write
accesses are still in progress. Dummy transaction completion is indicated by
incremented MxMR[MAD]. In order to enforce proper ordering between
updates to the MxMR register and the dummy accesses to the UPM memory
region, two rules must be followed:
1.) Since the result of any update to the MxMR/MDR register must be in effect
2.) The UPM memory region should have the same MMU settings as the
Exception Requests
before the dummy read or write to the UPM region, a write to MxMR/MDR
should be followed immediately by a read of MxMR/MDR.
memory region containing the MxMR configuration register; both
should be mapped by the MMU as cache-inhibited and guarded. This
prevents the e500 core from re-ordering a read of the UPM memory
around the read of MxMR. Once the programming of the UPM array is
complete the MMU setting for the associated address range can be set to
the proper mode for normal operation, such as cacheable and copyback.
NOTE
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