MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 319

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

8.2.1.9
The ECM error high address capture register (EEHADR) is shown in
Table 8-10
8.3
The following is a very general discussion of ECM operation.
8.3.1
Figure 8-1
request buses. Four request buses compete for access to the ECM, which can only process one request at
a time. The ECM uses two factors to select the winning request bus: the primary factor is requested
bandwidth and the secondary factor is longest waiting/least recently granted status. By default all
requesters start requesting low levels of bandwidth. A starvation avoidance algorithm ensures that low
bandwidth requesters make forward progress in the presence of high bandwidth requesters.The transaction
from the winning request bus competes with e500 core requests for the CCB and entry into the transaction
queue.
8.3.2
Figure 8-1
transaction queue. It handles arbitration for requests to use the CCB from the e500 core and the winning
request bus and consequently controls when these new transactions can enter the transaction queue.
Because the CCB bus operates most efficiently when it streams commands from one initiator, the CCB
arbiter alternates grants between streams of transactions from the e500 core and from the winner of the I/O
arbiter. The length of a stream (number of back-to-back transactions) is limited by the A_STRM_CNT
field in the EEBACR register. However, the arbiter also uses the priority of the requests to limit streaming.
If the priority of a new request is higher than that of a stream in progress, then the higher priority
transaction will interrupt the other stream. The priority of e500 transactions is set by the CPU_PRI field
Freescale Semiconductor
Offset 0x0_1E14
Reset
W
28–31
R
0–27
Bits
0
shows the I/O arbiter block that manages I/O-initiated address tenure requests arriving on the
shows the CCB arbiter block coordinating the entry of new transactions into the ECM’s
Functional Description
describes EEHADR fields.
I/O Arbiter
CCB Arbiter
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
ECM Error High Address Capture Register (EEHADR)
ADDR
Name
—
Figure 8-10. ECM Error High Address Capture Register (EEHADR)
Reserved
Address. Specifies the high-order 4 bits of the 36-bit address of the transaction.
Qualified by EEATR[VAL].
Table 8-10. EEHADR Field Descriptions
—
All zeros
Description
Figure
8-10.
e500 Coherency Module
Access: Read only
27 28
ADDR
31
8-9