MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 585

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

12.6.2.2
This section contains more detail on the sequence of events for a system bus read with the controller as
master:
When the SEC performs a transaction as master, it is possible for the intended slave to terminate the transfer
due to an error. The SEC’s transaction requests are posted to the MPC8533E target queue, after which the
MPC8533E takes responsibility for completing the transaction or signaling error. An error in an SEC
initiated transaction is also reported by the SEC via the channel interrupt status register. The host will be
able to determine which channel generated the interrupt by checking the ISR for the channel ERROR bit.
12.6.2.3
This section contains more detail on the sequence of events for an system bus write with the controller as
master:
While the controller is satisfying a requests from one channel, it can still acknowledge and queue requests
from the other channels.
12.6.2.4
The controller also acts as a bus slave. As a slave, the controller simply responds to read and write
commands from the bus. When a write command is received from the bus, the controller takes the data
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1. Channel asserts its bus read request to the controller.
2. Channel furnishes external read address, internal write address, and transfer length.
3. Controller sends request acknowledge to channel.
4. Controller asserts request to the system bus.
5. Controller waits for system bus read to begin.
6. When bus read begins, controller receives data from the master interface and performs a write to
7. Transfer continues until the bus read is completed and the controller has written all data to the
1. Channel asserts its bus write request to the controller.
2. Channel furnishes internal read address, external write address, and transfer length.
3. Controller sends request acknowledge to channel.
4. Controller performs a read from the appropriate internal address supplied by the channel, loads the
5. When the system bus becomes available, controller writes data from its FIFO to the master
the appropriate internal address supplied by the channel. Data may be realigned byte-wise by the
controller if either:
— the read did not begin on a 32-bit word boundary, or
— the previous write to an execution unit’s input FIFO did not end on a 32-bit word boundary.
appropriate internal address. The master interface continues making bus requests until the full data
length has been read.
write data into its FIFO, asserts a request to the system bus and waits for the system bus to become
available.
interface.
System Bus Master Reads
System Bus Master Writes
System Bus Slave Transactions (Reads and Writes)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Security Engine (SEC) 2.1
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