MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 204

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Core Complex Overview
All interrupts except machine check are ordered within the two categories of noncritical and critical, such
that only one interrupt of each category is reported, and when it is processed (taken), no program state is
lost. Because save/restore register pairs are serially reusable, program state may be lost when an unordered
interrupt is taken.
5.8.4
Core complex interrupt latency is defined as the number of core clocks between the sampling of the
interrupt signal as asserted and the initiation of the IVOR fetch (that is, the fetch of the first instruction in
the handler). Core complex interrupt latency is determinate unless a guarded load or a cache-inhibited
stwcx. is being executed, in which case the latency is indeterminate. The minimum latency is 3 core clocks
and the maximum is 8, not including the 2 bus clock cycles required to synchronize the interrupt signal
from the pad.
When an interrupt is taken, all instructions in the IQ are thrown away unless the oldest instruction is a
load/store instruction. That is, if an asynchronous interrupt is being serviced and the oldest instruction is
not a load/store instruction, the core complex goes straight from sampling the interrupt to ensuring a
recoverable state and issuing an exception. If a load/store instruction is oldest, the core complex waits
4 clocks before ensuring a recoverable state. During this time, any instruction finished by the LSU is
deallocated.
5.8.5
The registers associated with interrupt and exception handling are described in
5-20
MCSRR0 Machine check save/restore register 0—Used to store the address of the instruction that will execute after an rfmci
MCSRR1 Machine check save/restore register 1—Holds machine state on machine check interrupts and restores machine
Register
CSRR0
CSRR1
SRR0
SRR1
the critical enable bit, MSR[CE]. The embedded category defines the critical input, watchdog
timer, and machine check interrupts as critical interrupts, but the e500 implements a third set of
resources for the machine check interrupt, as described in
Save/restore register 0—Holds the address of the instruction causing the exception or the address of the instruction
that will execute after the rfi instruction.
Save/restore register 1—Holds machine state on noncritical interrupts and restores machine state after an rfi
instruction is executed.
Critical save/restore register 0—On critical interrupts, holds either the address of the instruction causing the
exception or the address of the instruction that will execute after the rfci instruction.
Critical save/restore register 1—Holds machine state on critical interrupts and restores machine state after an rfci
instruction is executed.
instruction is executed.
state (if recoverable) after an rfmci instruction is executed.
Upper Bound on Interrupt Latencies
Interrupt Registers
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Machine Check Interrupt Registers
Table 5-6. Interrupt Registers
Noncritical Interrupt Registers
Critical Interrupt Registers
Description
Table
5-6.
Table
Freescale Semiconductor
5-6.