MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 570

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
The channel can generate two types of done notification signals when it completes operation on a
descriptor—an interrupt and/or a writeback of the descriptor header. The done interrupt is enabled by the
CDIE bit and the writeback is enabled by the CDWE bit of the channel configuration register
(Table
The selected done notification can be performed at the end of processing of every descriptor, or only on
selected descriptors. If the NT field is 0 in the channel configuration register, then done notification is
performed after every descriptor. If the NT field is 1, then done notification is only performed on
descriptors in which the DN bit is set in the packet header
12.5.1
The SEC includes four channels that manage data and EU function. Each channel contains the following:
These registers are described in detail below.
12.5.1.1
These register contains nine operational bits permitting configuration of the channel as shown in
Figure
12-92
Address Channel_1 0x1108
Reset
Reset
•
•
•
•
•
•
W
W
R
R
12-50).
12-72.
A fetch FIFO, which holds a queue of pointers to descriptors waiting to be serviced
A configuration register, which allows the user a number of options for SEC event signaling.
Control registers containing information about the transaction in process
A status register containing an indication of the last unfulfilled bus request
A descriptor buffer memory used to store the active descriptor
Scatter and gather link table buffer memory used to store the active link table
Channel_2 0x1208
Channel_3 0x1308
Channel_4 0x1408
32
0
Channel Registers
Crypto-Channel Configuration Registers 1–4 (CCCR n )
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 12-51
Figure 12-72. Crypto-Channel Configuration Register (CCCR)
—
shows the DONE field that is written back in if writeback is enabled.
54
BS
55
—
IWSE
All zeros
All zeros
56
(Table
—
57
12-4).
EAE
58
CDWE AWSE
59
60
Freescale Semiconductor
Access: User read/write
NT
29
61
CDIE
CON
30
62
—
31
63
R