MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1085

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Table 18-27
caused by an outbound transaction from an internal source.
PEX_ERR_CAP_R0 for the case when the error is caused by an inbound transaction from an external
source (that is, PEX_ERR_CAP_STAT[GSID] = 0h02 for controller 1), is shown in
Table 18-28
inbound transaction from an external source.
Freescale Semiconductor
0–31
Bits
Offset 0xE28
Reset
18–22
23–31
16-17
0–15
Bits
W
R
describes the fields of the PCI Express error capture register 0 for the case when the error is
describes the fields of PEX_ERR_CAP_R0 for the case when the error is caused by an
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
Name
GH0
Figure 18-29. PCI Express Error Capture Register 0 (PEX_ERR_CAP_R0)
Table 18-27. PCI Express Error Capture Register 0 Field Descriptions
Table 18-28. PCI Express Error Capture Register 0 Field Descriptions
Name
TYPE
FMT
—
—
PCI Express 1st DW (4-byte) header. This field contains the PCI Express error packet’s 1st
DW (4-byte) header.
27–31
26–26
20–24
17–19
16
14–15
12–13
10–11
9
8
0–7
Reserved
PCI Express format. This field indicates the PCI Express packet format. See PCI
Express Spec 1.0a for more information on 3 or 4 DW (4-byte) header format.
PCI Express type. This field indicates the PCI express packet type. See PCI Express
Spec 1.0a for more information on 3 or 4 DW (4-byte) header format.
Reserved
type
fmt
Rsv
TC
Rsv
length[9:8]
Rsv
Attr
EP
TD
length[7:0]
Internal Source, Outbound Transaction
External Source, Inbound Transaction
External Source, Inbound Transaction
All zeros
GH0
Description
Description
PCI Express Interface Controller
Access: Read/Write
Figure
18-29.
31
18-37