MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 307

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

7.9.6
The L2 cache supports error checking and correcting (ECC) for the data path between the core master and
system memory. It detects all double-bit errors, detects all multi-bit errors within a nibble, and corrects all
single-bit errors. Other errors may be detected, but are not guaranteed to be corrected or detected.
Multiple-bit errors are always reported when error reporting is enabled. When a single-bit error occurs, the
single-bit error counter register is incremented, and its value compared to the single-bit error trigger register.
An error is reported when these values are equal. The single-bit error registers can be programmed such that
minor memory faults are corrected and ignored, but double- or multi-bit errors generate an interrupt.
The syndrome encodings for the ECC code are shown in
Freescale Semiconductor
Read
Read atomic
RWNITC
Kill
RWITM
RWITM atomic
RClaim
Transaction Type
Data
Bit
0
1
2
3
4
5
6
7
8
Error Checking and Correcting (ECC)
Table 7-28. State Transitions Due to System-Initiated Transactions (continued)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
•
•
•
•
•
•
•
•
•
1
•
•
•
wt
1
x
1
0
x
x
x
2
•
•
Syndrome Bit
ci
1
0
1
1
0
1
0
Table 7-29. L2 Cache ECC Syndrome Encoding
3
•
•
gbl
0
0
0
0
0
0
0
4
•
•
5
•
•
•
•
Initial L2
I/E/EL/T
State
EL/T
N/A
N/A
I//T
I/T
EL
EL
EL
I/E
E
E
T
6
I
•
7
•
•
•
•
Final L2
Same
Same
Same
Same
State
N/A
N/A
EL
EL
E
E
E
T
I
I
Table 7-29
Data
Bit
32
33
34
35
36
37
38
39
40
No L1/L2 effect
Read-and-clear-lock
No L1/L2 effect
Invalidate data, keep lock
0
•
•
and
1
•
•
Table
2
•
•
•
•
•
•
•
•
•
Syndrome Bit
Comments
7-30.
3
•
•
•
L2 Look-Aside Cache/SRAM
4
•
•
•
•
•
•
5
•
•
•
•
6
•
7
•
•
•
•
7-39