MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 888

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
15.6.4.1
Frame control blocks (FCBs) are 8-byte blocks of TOE control and/or status data that are passed between
software (driver and TCP/IP stack) and each eTSEC. A FCB always precedes the frame it applies to, and
is present only when TOE functions are being used. As
points to the initial data buffer and the FCB. The initial data buffer must be at least 8 bytes long to contain
the FCB without breaking it. Custom or received Ethernet preamble sequences also follow the FCB if
preambles are visible.
For TxBD rings, FCBs are assumed present when the TxBD[TOE/UN] bit is set by user software. The
eTSEC ignores the TxBD[TOE/UN] bit in all BDs other than those pointing to initial data buffers,
therefore FCBs must not be inserted in second and subsequent data buffers. Since TxBD[TOE/UN] can be
set under software discretion, TOE acceleration for transmit may be applied on a frame-by-frame basis.
In the case of RxBD rings, FCBs are inserted by the eTSEC whenever RCTRL[PRSDEP] is set to a
non-zero value. Only one FCB is inserted per frame, in the buffer pointed to by the RxBD with bit F set.
TOE acceleration for receive is enabled for all frames in this case.
15.6.4.2
TOE functions for transmit are defined by the contents of the Tx FCB.
definition for the Tx FCB.
15-158
Offset + 0
Offset + 2
Offset + 4
Offset + 6
Frame Control Blocks
Transmit Path Off-Load
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
VLN
BD
0
Figure 15-130. Location of Frame Control Blocks for TOE Parameters
IP
1
FCB
L3OS
L2 HDR
IP6
(last)
2
BD
Figure 15-131. Transmit Frame Control Block
TUP UDP CIP CTU NPH
3
L4OS
L4OS
L3 HDR
Frame data, first buffer
4
(first)
BD
5
L4 HDR
6
(last)
BD
7
VLCTL
Figure 15-130
PHCS
8
BD
9
Frame data, second buffer
BD ring
shows, the first BD of each frame
10
Figure 15-131
11
L3OS
12
Freescale Semiconductor
describes the
13
14
15