MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1279

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
0x2_46AC
0x2_46BC
0x2_46CC
0x2_46DC
0x2_46EC
0x2_468C
0x2_469C
0x2_46C0
0x2_46C4
0x2_46C8
0x2_46D0
0x2_46D4
0x2_46D8
0x2_46FC
0x2_4690
0x2_4694
0x2_4698
0x2_46A0
0x2_46A4
0x2_46A8
0x2_46B0
0x2_46B4
0x2_46B8
0x2_46E0
0x2_46E4
0x2_46E8
0x2_46F0
0x2_46F4
0x2_46F8
0x2_4700
0x2_4704
Offset
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
TR511—Transmit and receive 256- to 511-byte frame counter
TR1K—Transmit and receive 512- to 1023-byte frame
counter
TRMAX—Transmit and receive 1024- to 1518-byte frame
counter
TRMGV—Transmit and receive 1519- to 1522-byte good
VLAN frame count
RBYT—Receive byte counter
RPKT—Receive packet counter
RFCS—Receive FCS error counter
RMCA—Receive multicast packet counter
RBCA—Receive broadcast packet counter
RXCF—Receive control frame packet counter
RXPF—Receive PAUSE frame packet counter
RXUO—Receive unknown OP code counter
RALN—Receive alignment error counter
RFLR—Receive frame length error counter
RCDE—Receive code error counter
RCSE—Receive carrier sense error counter
RUND—Receive undersize packet counter
ROVR—Receive oversize packet counter
RFRG—Receive fragments counter
RJBR—Receive jabber counter
RDRP—Receive drop counter
TBYT—Transmit byte counter
TPKT—Transmit packet counter
TMCA—Transmit multicast packet counter
TBCA—Transmit broadcast packet counter
TXPF—Transmit PAUSE control frame counter
TDFR—Transmit deferral packet counter
TEDF—Transmit excessive deferral packet counter
TSCL—Transmit single collision packet counter
TMCL—Transmit multiple collision packet counter
TLCL—Transmit late collision packet counter
Table B-1. Memory Map (continued)
Register
eTSEC Transmit Counters
eTSEC Receive Counters
Complete List of Configuration, Control, and Status Registers
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
15.5.3.6.10/15-84
15.5.3.6.11/15-84
15.5.3.6.12/15-85
15.5.3.6.13/15-85
15.5.3.6.14/15-86
15.5.3.6.15/15-86
15.5.3.6.16/15-87
15.5.3.6.17/15-87
15.5.3.6.18/15-88
15.5.3.6.19/15-88
15.5.3.6.20/15-89
15.5.3.6.21/15-89
15.5.3.6.22/15-90
15.5.3.6.23/15-90
15.5.3.6.24/15-91
15.5.3.6.25/15-91
15.5.3.6.26/15-92
15.5.3.6.27/15-92
15.5.3.6.28/15-93
15.5.3.6.29/15-93
15.5.3.6.30/15-94
15.5.3.6.31/15-94
15.5.3.6.32/15-95
15.5.3.6.33/15-95
15.5.3.6.34/15-96
15.5.3.6.4/15-81
15.5.3.6.5/15-81
15.5.3.6.6/15-82
15.5.3.6.7/15-82
15.5.3.6.8/15-83
15.5.3.6.9/15-83
Section/Page
B-21