MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1094

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PCI Express Interface Controller
18.3.8.1.4
The status register, shown in
events.
.
18-46
The definition of each bit is given in
Bits
15
14
13
12
11
Bits
Offset 0x06
Reset
Reset
1
0
W
W
R
R
Signaled system
Detected parity
master-abort
target-abort
target-abort
I/O space
Received
Received
parity error
Signaled
Memory
Detected
Name
space
Name
error
error
w1c
15
—
0
7
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
1
1
PCI Express Status Register—Offset 0x06
Table 18-37. PCI Express Command Register Field Descriptions (continued)
1
1
1
Controls whether this PCI Express device (as a target) responds to memory accesses.
0 This PCI Express device does not respond to PCI Express memory space accesses.
1 This PCI Express device responds to PCI Express memory space accesses.
EP mode: Clearing this bit will prevent the device from accepting any memory transaction.
RC mode: This bit is ignored. It does not affect outbound memory transaction
I/O space.
0 This PCI Express device (as a target) does not respond to PCI Express I/O space accesses.
1 This PCI Express device (as a target) does respond to PCI Express I/O space accesses.
EP mode: Clearing this bit will prevent the device from accepting any IO transaction. Note that this bit is
RC mode: This bit is ignored. It does not affect outbound IO transaction.
system error
Set whenever a device receives a poisoned TLP regardless of the state of bit 6 in the command register.
Set whenever a device sends a ERR_FATAL or ERR_NONFATAL message and the SERR enable bit in
the command register is set.
Set whenever a requestor receives a completion with unsupported request completion status.
Set whenever a device receives a completion with completer abort completion status.
Set whenever a device completes a request using completer abort completion status.
a don’t care in EP mode since the device does not support IO transaction.
Signaled
Table 18-38. PCI Express Status Register Field Descriptions
w1c
—
14
0
6
Figure
Figure 18-40. PCI Express Status Register
master-abort
Received
w1c
18-40, is used to record status information for PCI Express related
—
13
0
5
Table
18-38.
target-abort
Capabilities
Received
w1c
list
12
1
4
All zeros
target-abort
Description
Signaled
Interrupt
Description
Status
w1c
11
3
0
10
0
2
—
Freescale Semiconductor
—
0
9
Access: Mixed
Master data
parity error
w1c
0
8
0