MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 867

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Table 15-126
15.6.2
This section describes how to connect an eTSEC to third-party communication devices, including users’
ASICs and FPGAs, via the FIFO interface.
Each eTSEC provides an 8-bit full-duplex packet FIFO interface port that bypasses the Ethernet MAC, but
re-uses the GMII signals. As a result, the FIFO interface normally does not impose the overheads of
Ethernet framing. The FIFO interface operates synchronously, at a maximum frequency defined by a ratio
of 4.2:1 (platform:TxClk) in GMII mode and 3.2:1 (platform:TxClk) in encoded mode providing OC-48
full-duplex transfer rates. For example, a FIFO frequency of 127 MHz in GMII mode requires a platform
frequency of 533 MHz; a FIFO frequency of 200 MHz in encoded mode requires a platform frequency of
667 MHz; a FIFO frequency of 167 MHz in encoded mode requires a platform frequency of 533 MHz.
The eTSEC Tx and Rx FIFOs, TOE functions, and DMA continue to be used in packet FIFO mode.
The ECNTRL[FIFM] bit determines whether eTSEC is communicating with its Ethernet MAC or FIFO
interface.
Freescale Semiconductor
Bare IP packets—with an optional 32-bit CRC check sequence—can be transferred to the eTSEC directly.
•
8-bit packet FIFO
— The GMII signals of each eTSEC can be used to create a FIFO port, therefore eTSEC can
— The data signals of GMII and 8-bit FIFO remain the same. The data valid (RX_DV, TX_EN)
support up to simultaneous 8-bit FIFO interfaces Choosing between 8-bit FIFO and Ethernet
affects each eTSEC independently, therefore a mix of FIFO and Ethernet interfaces can be
configured.
and error (RX_ER, TX_ER) signals are used to signal framing information. If required, the
collision (COL) and carrier sense (CRS) signals can be used in an encoded mode to provide
link-level flow control.
Connecting to FIFO Interfaces
describes the signals shared by all interfaces.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
GTX_CLK125
EC_MDIO
EC_MDC
Signals
Sum
Table 15-126. Shared Signals
I/O
I/O
O
I
Signals
No. of
1
1
1
Management interface clock
Management interface I/O
Reference clock
Function
Enhanced Three-Speed Ethernet Controllers
15-137