MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1273

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
0x2_4008–
0x2_400C
0x2_401C
0x2_402C
0x2_4000
0x2_4004
0x2_4010
0x2_4014
0x2_4018
0x2_4020
0x2_4024
0x2_4028
0x2C8
0x2BC
0x2FC
0x28C
0x29C
0x2A0
0x2A4
0x2A8
0x2B0
0x2B4
0x2B8
0x2C0
0x2C4
0x284
0x288
0x290
0x294
0x298
0x300
Offset
–
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
SR3—DMA 3 status register
ECLNDAR3—DMA 3 current link descriptor extended
address register
CLNDAR3—DMA 3 current link descriptor address register
SATR3—DMA 3 source attributes register
SAR3—DMA 3 source address register
DATR3—DMA 3 destination attributes register
DAR3—DMA 3 destination address register
BCR3—DMA 3 byte count register
ENLNDAR3—DMA 3 next link descriptor extended address
register
NLNDAR3—DMA 3 next link descriptor address register
ECLSDAR3—DMA 3 current list descriptor extended address
register
CLSDAR3—DMA 3 current list descriptor address register
ENLSDAR3—DMA 3 next list descriptor extended address
register
NLSDAR3—DMA 3 next list descriptor address register
SSR3—DMA 3 source stride register
DSR3—DMA 3 destination stride register
Reserved
DGSR—DMA general status register
TSEC_ID*—Controller ID register
TSEC_ID2*—Controller ID register
Reserved
IEVENT—Interrupt event register
IMASK—Interrupt mask register
EDIS—Error disabled register
Reserved
ECNTRL—Ethernet control register
Reserved
PTV—Pause time value register
DMACTRL—DMA control register
eTSEC n General Control and Status Registers
Table B-1. Memory Map (continued)
Register
eTSEC Registers
Complete List of Configuration, Control, and Status Registers
4
Access
Mixed
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
R
R
R
R
R
R
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0124_0000
0x0030_00F0
0x0030_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
—
15.5.3.1.1/15-22
15.5.3.1.2/15-23
15.5.3.1.3/15-24
15.5.3.1.4/15-28
15.5.3.1.5/15-30
15.5.3.1.6/15-31
15.5.3.1.7/15-33
15.5.3.1.8/15-34
16.3.1.10/16-21
16.3.1.10/16-21
16.3.1.11/16-22
16.3.1.11/16-22
16.3.1.12/16-22
16.3.1.13/16-23
16.3.1.14/16-24
16.3.1.2/16-12
16.3.1.3/16-13
16.3.1.3/16-13
16.3.1.4/16-15
16.3.1.5/16-16
16.3.1.6/16-17
16.3.1.7/16-18
16.3.1.8/16-19
16.3.1.9/16-19
16.3.1.9/16-19
Section/Page
—
—
—
—
B-15