MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 781

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MPC8533EVTAQGA

Manufacturer Part Number
MPC8533EVTAQGA
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTAQGA

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.0GHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
783-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8533EVTAQGA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Writing 1 to any bit of this register clears it. Software should clear the QHLT bit to take eTSEC’s receiver
function out of halt state for the associated queue.
register.
Table 15-27
Freescale Semiconductor
Offset eTSEC1:0x2_4304; eTSEC3:0x2_6304
Reset
Reset
Bits
0–7
10
11
12
8
9
W
W
R
R
16
0
QHLT0 RxBD queue 0 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
QHLT1 RxBD queue 1 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
QHLT2 RxBD queue 2 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
QHLT3 RxBD queue 3 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
QHLT4 RxBD queue 4 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
Name
describes the fields of the RSTAT register.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
not cause a QHLT0 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
not cause a QHLT1 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
not cause a QHLT2 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
not cause a QHLT3 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
not cause a QHLT4 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
Figure 15-23. RSTAT Register Definition
Table 15-27. RSTAT Field Descriptions
23
7
QHLT0 QHLT1 QHLT2 QHLT3 QHLT4 QHLT5 QHLT6 QHLT7
RXF0
w1c
w1c
24
8
Figure 15-23
All zeros
All zeros
RXF1
w1c
w1c
Description
25
9
RXF2
w1c
w1c
10
26
describes the definition for the RSTAT
RXF3
w1c
w1c
Enhanced Three-Speed Ethernet Controllers
11
27
RXF4
w1c
w1c
12
28
RXF5
w1c
w1c
13
29
RXF6
w1c
w1c
14
30
Access: w1c
RXF7
w1c
w1c
15-51
15
31

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