MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 375

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
Activate
Precharge select
logical bank
Precharge all logical
banks
Read
Read with
auto-precharge
Write
•
•
•
•
Operation
Write—Latches column address and transfers data from the data pins to the selected sense
amplifier as determined by the column address. During each succeeding clock edge, additional data
is transferred to the sense amplifiers from the data pins without additional write commands. The
amount of data transferred is determined by the data masks and the burst size, which is set to four
by the DDR memory controller.
Refresh (similar to MCAS before MRAS)—Causes a row to be read in all logical banks (JEDEC
SDRAM) as determined by the refresh row address counter. This refresh row address counter is
internal to the SDRAM. After being read, the row is automatically rewritten in the memory array.
All logical banks must be in a precharged state before executing a refresh. The memory controller
also supports posted refreshes, where several refreshes may be executed at once, and the refresh
interval may be extended.
Mode register set (for configuration)—Allows setting of DDR SDRAM options. These options are:
MCAS latency, additive latency (for DDR2), write recovery (for DDR2), burst type, and burst
length. MCAS latency may be chosen as provided by the preferred SDRAM (some SDRAMs
provide MCAS latency {1,2,3}, some provide MCAS latency {1,2,3,4,5}, etc.). Burst type is
always sequential. Although some SDRAMs provide burst lengths of 1, 2, 4, 8, and page size, this
memory controller supports a burst length of 4. A burst length of 8 is supported for DDR1memory
only. For DDR2 in 32-bit bus mode, all 32-byte burst accesses from the platform are split into two
16-byte (that is, 4 beat) accesses to the SDRAMs in the memory controller. The mode register set
command is performed by the DDR memory controller during system initialization. Parameters
such as mode register data, MCAS latency, burst length, and burst type, are set by software in
DDR_SDRAM_MODE[SDMODE] and transferred to the SDRAM array by the DDR memory
controller after DDR_SDRAM_CFG[MEM_EN] is set. If DDR_SDRAM_CFG[BI] is set to
bypass the automatic initialization, then the MODE registers can be configured through software
via use of the DDR_SDRAM_MD_CNTL register.
Self refresh (for long periods of standby)—Used when the device is in standby for very long
periods of time. Automatically generates internal refresh cycles to keep the data in all memory
banks refreshed. Before execution of this command, the DDR controller will place all logical banks
in a precharged state.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Prev.
CKE
H
H
H
H
H
H
Current
CKE
H
H
H
H
H
H
Table 9-46. DDR SDRAM Command Table
MCS MRAS MCAS MWE
L
L
L
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
Logical bank select
Logical bank select
Logical bank select
Logical bank select
Logical bank select
MBA
X
MA10
Row
H
H
L
L
L
DDR Memory Controller
Column
Column
Column
Row
MA
X
X
9-53