MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 809

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Table 15-52
15.5.3.6
This section describes the MIB registers. The eTSEC RMON module has 37 separate statistics counters,
which simply count or accumulate statistical events that occur as packets transmitted and received. These
counters support RMON MIB group 1, RMON MIB group 2 if table counters, RMON MIB group 3,
RMON MIB group 9, RMON MIB 2, and the 802.3 Ethernet MIB.
An interrupt can be generated upon any one counter’s rollover condition via a carry interrupt output from
the RMON. Each counter’s rollover condition can be discretely masked from causing an interrupt by
internal masking registers. In addition, each individual counter value may be reset on read access, or all
counters may be simultaneously reset by setting ECNTRL[CLRCNT].
The majority of MIB counters are Ethernet-specific.
In FIFO modes, only the following registers are updated:
Note: RMON counters will not comprehend custom VLAN tagged frames. Affected counters include
TRMGV, RMCA, RBCA, RXCF, RXPF, RXUO, RALN, RFLR, ROVR, RJBR, TMCA, TBCA, TXPF,
TXCF. Specifically, custom VLAN tagged frames will not be afforded the ability to be greater than 1518,
as the IEEE standard tagged frames will be.
15.5.3.6.1
Figure 15-52
Freescale Semiconductor
Offset eTSEC1:0x2_4680; eTSEC3:0x2_6680
Reset
•
•
16–31
W
8–15 Exact Match Address, 1st Octet
R
0–7
Transmit: TBYT, TPKT, TDRP
Receive: RBYT, RPKT, RFCS
Bit
0
Exact Match Address, 2nd Octet
describes the fields of a MACxADDR2 register.
MIB Registers
describes the definition for the TR64 register.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Transmit and Receive 64-Byte Frame Counter (TR64)
Figure 15-52. Transmit and Receive 64-Byte Frame Register Definition
Table 15-54. MAC01ADDR2–MAC15ADDR2 Field Descriptions
—
Name
—
9
10
This field holds the second octet of the exact match address. The
second octet (destination address bits 8–15) defaults to a value of
0x0.
This field holds the first octet of the exact match address. The first
octet (destination address bits 0–7) defaults to a value of 0x0.
Reserved
All zeros
Description
TR64
Enhanced Three-Speed Ethernet Controllers
Access: Read/Write
15-79
31