MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 597

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

13.2
This section contains a signal overview and detailed signal descriptions.
13.2.1
Table 13-1
prepended with the UART_ prefix as shown in the table, the functional (abbreviated) signal names are
often used throughout this chapter.
13.2.2
The DUART signals are described in detail in
Freescale Semiconductor
UART_SOUT[0:1]
UART_CTS[0:1]
UART_SIN[0:1]
Signal
UART_SOUT[0:1]
UART_CTS[0:1]
UART_RTS[0:1]
UART_SIN[0:1]
Signal Name
External Signal Descriptions
summarizes the DUART signals. Note that although the actual device signal names are
Signal Overview
Detailed Signal Descriptions
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
I/O
O
I
I
Serial data in. Data is received on the receivers of UART0 and UART1 through its respective serial
data input signal, with the least-significant bit received first.
Serial data out. The serial data output signals for the UART0 and UART1 are set ('mark' condition)
when the transmitter is disabled, idle, or operating in the local loopback mode. Data is shifted out on
these signals, with the least significant bit transmitted first.
Clear to send. These active-low inputs are the clear-to-send inputs. They are connected to the
respective RTS outputs of the other UART devices on the bus. They can be programmed to generate
an interrupt on change-of-state of the signal.
Meaning
Meaning
Meaning
Timing Assertion/Negation—An internal logic sample signal, rxcnt , uses the frequency of the
Timing Assertion/Negation— An internal logic sample signal, rxcnt , uses the frequency of the
Timing Assertion/Negation—Sampled at the rising edge of every CCB clock.
Table 13-2. DUART Signals—Detailed Signal Descriptions
State
State
State
I/O
O
O
I
I
Asserted/Negated—Represents the data being received on the UART interface.
Asserted/Negated—Represents the data being transmitted on the respective UART
Asserted/Negated—Represent the clear to send condition for their respective UART.
baud-rate generator to sample the data on SIN.
interface.
baud-rate generator to update and drive the data on SOUT.
Table 13-1. DUART Signal Overview
Pins
2
2
2
2
Reset
Value
1
1
1
1
Table
Serial in data UART0 and UART1
Serial out data UART0 and UART1
Clear to send UART0 and UART1
Request to send UART0 and UART1
13-2.
Description
State Meaning
DUART
13-3