MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 760

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MPC8533EVTAQGA

Manufacturer Part Number
MPC8533EVTAQGA
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTAQGA

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.0GHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
783-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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Part Number
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Quantity
Price
Part Number:
MPC8533EVTAQGA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Enhanced Three-Speed Ethernet Controllers
15.5.3.1.5
Figure 15-6
disable an error interruption, possibly to avoid spurious error indications external to the eTSECs.
Table 15-9
15-30
Offset eTSEC1:0x2_4018; eTSEC3:0x2_6018
Reset
Reset
10–12
Bits
0–1
4–6
13
2
3
7
8
9
W
W
R
R
16
0
EBERRDIS Ethernet controller bus error disable.
BABTDIS
BSYDIS
TXEDIS
LCDIS
Name
describes the fields of the EDIS register.
describes the definition for the EDIS register. The error disabled register allows the user to
1
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Error Disabled Register (EDIS)
BSYDIS EBERRDIS
2
Reserved
Busy disable.
0 Allow eTSEC to report IEVENT[BSY] status and halt buffer descriptor queue if BSY condition occurs.
1 Do not set IEVENT[BSY] and do not halt buffer descriptor queue if BSY condition occurs.
0 Allow eTSEC to report IEVENT[EBERR] status and halt buffer descriptor queue if EBERR condition
1 Do not set IEVENT[EBERR] and do not halt buffer descriptor queue if EBERR condition occurs.
Reserved
Babbling transmit error disable.
0 Allow eTSEC to report IEVENT[BABT] status and set the buffer descriptor TR field.
1 Do not set IEVENT[BABT] nor the buffer descriptor TR field.
Reserved
Transmit error disable.
0 Allow eTSEC to report IEVENT[TXE] status.
1 Do not set IEVENT[TXE] if TXE condition occurs.
Reserved
Late collision disable.
0 Allow eTSEC to report IEVENT[LC] status, set the buffer descriptor LC field, and halt buffer descriptor
1 Do not set IEVENT[LC] nor the buffer descriptor LC field, and do not halt buffer descriptor queue if
occurs.
queue if LC condition occurs.
LC condition occurs.
3
Figure 15-6. EDIS Register Definition
Table 15-9. EDIS Field Descriptions
4
6
BABTDIS — TXEDIS
7
All zeros
All zeros
8
Description
9
10
27
FIRDIS FIQDIS DPEDIS PERRDIS
12
28
LCDIS CRLDIS XFUNDIS
13
29
Freescale Semiconductor
Access: Read/Write
14
30
15
31

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