MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 549

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

12.4.6.5
AESU status register is a read-only register that reflects the state of six status outputs. Writing to this
location will result in an address error being reflected in the AESU interrupt status register.
Table 12-41
Freescale Semiconductor
40–47
48–55
56–57
59–60 ICCR Integrity check comparison result
Address AESU 0x3_4028
0–39
Bits
58
61
62
63
Reset
W
R
Name
HALT Halt. Indicates that the AESU has halted due to an error.
OFL
IFL
RD
—
—
0
IE
ID
describes the AESU status register fields.
Reserved
The number of dwords currently in the output FIFO
The number of dwords currently in the input FIFO
Reserved
0 AESU not halted
1 AESU halted
Note: Because the error causing the AESU to stop operating may be masked before reaching the interrupt
00 No integrity check comparison was performed.
01 The integrity check comparison passed.
10 The integrity check comparison failed.
11 Reserved
A passed or failed result is generated only if ICV checking is enabled and the cipher mode selected is CCM with
ICV comparison
Interrupt error. This status bit reflects the state of the ERROR interrupt signal, as sampled by the controller
interrupt status register
0 AESU is not signaling error
1 AESU is signaling error
Interrupt done. This status bit reflects the state of the DONE interrupt signal, as sampled by the controller
interrupt status register
0 AESU is not signaling done
1 AESU is signaling done
Reset done. This status bit, when high, indicates that AESU has completed its reset sequence, as reflected in
the signal sampled by the appropriate channel.
0 Reset in progress
1 Reset done
Note: Reset done resets to 0, but has typically switched to 1 by the time a user checks the register, indicating
AESU Status Register (AESUSR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
status register, the AESU interrupt status register is used to provide a second source of information
regarding errors preventing normal operation.
the EU is ready for operation.
—
Table 12-41. AESU Status Register Field Descriptions
(Section 12.6.5.3, “Interrupt Status Register
(Section 12.6.5.3, “Interrupt Status Register
Figure 12-51. AESU Status Register
39 40
OFL
47 48
All zeros
IFL
Description
55
56
—
57
(ISR)”).
(ISR)”).
HALT
58
59
ICCR
60
Security Engine (SEC) 2.1
Access: Read-only
61
IE
ID
62
12-71
RD
63