MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 24

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Paragraph
Number
14.3.1.4
14.3.1.5
14.3.1.6
14.3.1.7
14.3.1.8
14.3.1.9
14.3.1.10
14.3.1.11
14.3.1.12
14.3.1.13
14.3.1.14
14.3.1.15
14.3.1.16
14.4
14.4.1
14.4.1.1
14.4.1.2
14.4.1.3
14.4.1.4
14.4.1.5
14.4.1.6
14.4.1.7
14.4.2
14.4.2.1
14.4.2.2
14.4.2.2.1
14.4.2.2.2
14.4.2.2.3
14.4.2.2.4
14.4.2.2.5
14.4.2.3
14.4.2.4
14.4.3
14.4.3.1
14.4.3.2
14.4.3.3
14.4.3.4
14.4.3.5
14.4.3.6
14.4.3.7
14.4.3.7.1
xxiv
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Functional Description................................................................................................. 14-32
Basic Architecture.................................................................................................... 14-33
General-Purpose Chip-Select Machine (GPCM)..................................................... 14-36
SDRAM Machine .................................................................................................... 14-47
UPM Mode Registers (MxMR) ........................................................................... 14-17
Memory Refresh Timer Prescaler Register (MRTPR) ........................................ 14-20
UPM Data Register (MDR) ................................................................................. 14-20
SDRAM Machine Mode Register (LSDMR) ...................................................... 14-21
UPM Refresh Timer (LURT)............................................................................... 14-23
SDRAM Refresh Timer (LSRT).......................................................................... 14-23
Transfer Error Status Register (LTESR) .............................................................. 14-24
Transfer Error Check Disable Register (LTEDR)................................................ 14-25
Transfer Error Interrupt Enable Register (LTEIR) .............................................. 14-26
Transfer Error Attributes Register (LTEATR) ..................................................... 14-27
Transfer Error Address Register (LTEAR).......................................................... 14-29
Local Bus Configuration Register (LBCR) ......................................................... 14-29
Clock Ratio Register (LCRR).............................................................................. 14-30
Address and Address Space Checking ................................................................ 14-33
External Address Latch Enable Signal (LALE) .................................................. 14-33
Data Transfer Acknowledge (TA) ....................................................................... 14-34
Data Buffer Control (LBCTL)............................................................................. 14-35
Atomic Operation ................................................................................................ 14-35
Parity Generation and Checking (LDP)............................................................... 14-36
Bus Monitor ......................................................................................................... 14-36
Timing Configuration .......................................................................................... 14-37
Chip-Select Assertion Timing ............................................................................. 14-39
External Access Termination (LGTA) ................................................................. 14-46
Boot Chip-Select Operation................................................................................. 14-46
Supported SDRAM Configurations..................................................................... 14-47
SDRAM Power-On Initialization ........................................................................ 14-48
Intel PC133 and JEDEC-Standard SDRAM Interface Commands ..................... 14-49
Page Hit Checking ............................................................................................... 14-50
Page Management................................................................................................ 14-50
SDRAM Address Multiplexing ........................................................................... 14-50
SDRAM Device-Specific Parameters.................................................................. 14-51
Programmable Wait State Configuration......................................................... 14-40
Chip-Select and Write Enable Negation Timing ............................................. 14-40
Relaxed Timing ............................................................................................... 14-41
Output Enable (LOE) Timing.......................................................................... 14-43
Extended Hold Time on Read Accesses .......................................................... 14-43
Precharge-to-Activate Interval......................................................................... 14-52
Contents
Title
Freescale Semiconductor
Number
Page