MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 376

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DDR Memory Controller
9.5.4
The DDR memory controller supports four-beat bursts to SDRAM. For single-beat reads, the DDR
memory controller performs a four- (or eight-) beat burst read, but ignores the last three (or seven) beats.
Single-beat writes are performed by masking the last three (or seven) beats of the four- (or eight-) beat
burst using the data mask MDM[0:8]. If ECC is disabled, writes smaller than double words are performed
by appropriately activating the data mask. If ECC is enabled, the controller performs a read-modify write.
To accommodate available memory technologies across a wide spectrum of operating frequencies, the
DDR memory controller allows the setting of the intervals defined in
memory clock cycle, except for CASLAT, which can be programmed with 1/2 clock granularity.
9-54
Write with
auto-precharge
Mode register set
Auto refresh
Self refresh
Timing Intervals
ACTTOPRE
ACTTOACT
PRETOACT
ACTTORW
BSTOPRE
Operation
CASLAT
DDR SDRAM Interface Timing
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
If a second read or write is pending, reads shorter than four beats are not
terminated early even if some data is irrelevant.
The number of clock cycles from a bank-activate command until another bank-activate command within
a physical bank. This interval is listed in the AC specifications of the SDRAM as t
The number of clock cycles from an activate command until a precharge command is allowed. This
interval is listed in the AC specifications of the SDRAM as t
The number of clock cycles from an activate command until a read or write command is allowed. This
interval is listed in the AC specifications of the SDRAM as t
The number of clock cycles to maintain a page open after an access. The page open duration counter
is reloaded with BSTOPRE each time the page is accessed (including page hits). When the counter
expires, the open page is closed with a SDRAM precharge bank command as soon as possible.
Used in conjunction with additive latency to obtain the READ latency. The number of clock cycles
between the registration of a READ command by the SDRAM and the availability of the first piece of
output data. If a READ command is registered at clock edge
data is available nominally coincident with clock edge
allowed. This interval is listed in the AC specifications of the SDRAM as t
The number of clock cycles from a precharge command until an activate or a refresh command is
Prev.
CKE
H
H
H
H
Current
Table 9-46. DDR SDRAM Command Table (continued)
CKE
Table 9-47. DDR SDRAM Interface Timing Intervals
H
H
H
L
MCS MRAS MCAS MWE
L
L
L
L
H
L
L
L
NOTE
L
L
L
L
H
H
L
L
Definition
Logical bank select
n
+
Opcode
MBA
m
RAS
RCD
X
X
Table 9-47
n
.
, and the read latency is
.
.
RP
Opcode Opcode and mode
MA10
with granularity of one
.
H
X
X
Freescale Semiconductor
RRD
.
m
Column
clocks, the
MA
X
X