MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 651

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
14.4.1
Basic Architecture
The following sections describe the basic architecture of the LBC.
14.4.1.1
Address and Address Space Checking
The defined base addresses are written to the BRn registers, while the corresponding address masks are
written to the ORn registers. Each time a local bus access is requested, the internal transaction address is
compared with each bank. Addresses are decoded by comparing the 19 msbs of the address, masked by
ORn[XAM] and ORn[AM], with the base address for each bank (BRn[XBA] and BRn[BA]). If a match
is found on a memory controller bank, the attributes defined in the BRn and ORn for that bank are used to
control the memory access. If a match is found in more than one bank, the lowest-numbered bank handles
the memory access (that is, bank 0 has priority over bank 1).
14.4.1.2
External Address Latch Enable Signal (LALE)
The local bus uses a multiplexed address/data bus. Therefore, the LBC must distinguish between address
and data phases, which take place on the same bus (LAD[0:31] signals). The LALE signal, when asserted,
signifies an address phase during which the LBC drives the memory address on the LAD[0:31] signals.
An external address latch uses this signal to capture the address and provide it to the address signals of the
memory or peripheral device. When LALE is negated, LAD[0:31] then serves as the (bidirectional) data
bus for the access. Any address phase initiates the assertion of LALE, which has a programmable duration
of between 1 and 4 bus clock cycles.
To ensure adequate hold time on the external address latch, LALE negates earlier than the address changes
on LAD[0:31] during address phases. By default, LALE negates earlier by two platform clock periods
(which, divided by LCRR[CLKDIV], yields the local bus clock). For example, if the LBC is operating at
666 MHz internally, then an additional 3 ns of address hold time is introduced. However, when
LCRR[CLKDIV] = 2 (clock ratio of 4) and the LCLK frequency exceeds 100 MHz, the duration of the
shortened LALE pulse may not meet the minimum latch enable pulse width specifications of some latches.
In such cases, setting LBCR[AHD] = 1 increases the LALE pulse width by one platform clock cycle, and
decreases the address hold time by the same amount. At 666 MHz and with LCRR[CLKDIV] = 2 (clock
ratio of 4), the duration of LALE would then be 4.5 ns, with 1.5 ns of hold time. If both longer hold time
and longer LALE pulse duration are needed, then the address phase can be extended using the ORn[EAD]
and LCRR[EADC] fields, and the LBCR[AHD] bit can be left at 0. However, this will add latency to all
address tenures.
The frequency of LALE assertion varies across the three memory controllers. For GPCM, every assertion
of LCSn is considered an independent access, and accordingly, LALE asserts prior to each such access.
For example, GPCM driving an 8-bit port would assert LALE and LCSn 32 times in order to satisfy a
32-byte cache line transfer. The SDRAM controller asserts LALE only to initiate a burst transfer with a
starting address, therefore no more than one assertion of LALE may be required for SDRAM to transfer a
32-byte cache line through a 32-bit port. In the case of UPM, the frequency of LALE assertion depends on
how the UPM RAM is programmed. UPM single accesses typically assert LALE once, on
commencement, but it is possible to program UPM to assert LALE several times, and to change the values
of LA[27:31] with and without LALE being involved. In general, when using the GPCM and SDRAM
controllers it is not necessary to use LA[27:31] if a sufficiently wide latch is used to capture the entire
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor
14-33