MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 485

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

128 bits (in byte increments), providing a wide range of security strengths. ARC4 is a symmetric
algorithm, meaning each of the two communicating parties share the same key.
For more information, refer to
12.1.2.4
The MDEU computes a single message digest (or hash or integrity check) value of all the data presented
on the input bus, using either the MD5, SHA-1, SHA-225 or SHA-256 algorithms for bulk data hashing.
With any hash algorithm, the larger message is mapped onto a smaller output space; therefore collisions
are possible, albeit not probable. The 160-bit hash value is a sufficiently large space such that collisions
are extremely rare. The security of the hash function is based on the difficulty of locating collisions. That
is, it is computationally infeasible to construct two distinct but similar messages that produce the same
hash output.
For more information, refer to
12.1.2.5
The RNG is a functional block capable of generating 64-bit random numbers. It is designed to comply with
FIPS 140-1 standards for randomness and non-determinism.
Because many cryptographic algorithms use random numbers as a source for generating a secret value (a
nonce), it is desirable to have a private RNG for use by the SEC. The anonymity of each random number
must be maintained, as well as the unpredictability of the next random number. The FIPS-140
common-criteria compliant private RNG allows the system to develop random challenges or random
secret keys. The secret key can thus remain hidden from even the high-level application code, providing
an added measure of physical security.
For more information, refer to
12.1.2.6
The AESU is used to accelerate bulk data encryption/decryption in compliance with the Advanced
Encryption Standard Rijndael algorithm. The AESU executes on 128 bit blocks with a choice of key sizes:
128, 192, or 256 bits.
AESA is a symmetric-key algorithm, the sender and receiver use the same key for both encryption and
decryption. The session key and initialization vector (IV) are supplied to the AESU module prior to
encryption. The processor supplies data to the module that is processed as 128 bit input. The AESU
operates in ECB, CBC, CTR, and CCM modes.
Freescale Semiconductor
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The MD5 generates a 128-bit hash, and the algorithm is specified in RFC 1321.
SHA-1 is a 160-bit hash function, specified by the ANSI X9.30-2 and FIPS 180-1 standards.
SHA-224 and SHA-256 are cryptographic hash functions that provide integrity protection against
collision attacks.
The MDEU also supports HMAC computations, as specified in RFC 2104.
Message Digest Execution Unit (MDEU)
Random Number Generator (RNG)
Advanced Encryption Standard Execution Unit (AESU)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Section 12.4.3, “ARC Four Execution Unit (AFEU).”
Section 12.4.4, “Message Digest Execution Unit (MDEU).”
Section 12.4.5, “Random Number Generator (RNG).”
Security Engine (SEC) 2.1
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