MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 178

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Reset, Clocking, and Initialization
4.4.3.16
The PCI I/O impedance configuration inputs, shown in
drivers for the respective interfaces. Note that the values latched on these signals during POR are
accessible through PORIMPSCR, described in
Register (PORIMPSCR).”
4.4.3.17
The PCI arbiter configuration inputs, shown in
value latched on these signals during POR are accessible through the PORDEVSR described in
Section 19.4.1.4, “POR Device Status Register (PORDEVSR).”
4.4.3.18
The memory debug configuration input, shown in
memory controller) are driven onto the MSRCID and MDVAL debug signals. Note that the value latched
on this signal during POR is accessible through the memory-mapped PORDBGMSR (POR debug mode
register) described in
4.4.3.19
The DDR debug configuration input, shown in
in which the DDR SDRAM source ID field and data valid strobe are driven onto the ECC pins. ECC
checking and generation are disabled in this case. ECC signals driven from the SDRAMs must be
electrically disconnected from the ECC I/O pins of the MPC8533E in this mode.
4-20
Functional Signal
Functional
PCI_GNT2
Functional
Default (1)
Default (1)
MSRCID0
Signal
Signal
PCI_GNT1
Default (1)
Reset Configuration
PCI I/O Impedance
PCI Arbiter Configuration
Memory Debug Configuration
DDR Debug Configuration
Reset Configuration
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
cfg_mem_debug
cfg_pci_arb
Name
Reset Configuration
Name
Section 19.4.1.5, “POR Debug Mode Status Register (PORDBGMSR).”
cfg_pci_impd
Name
(Binary)
Table 4-26. Memory Debug Configuration
Value
(Binary)
Table 4-25. PCI Arbiter Configuration
0
1
Value
0
1
Table 4-24. PCI I/O Impedance
The on-chip PCI arbiter is disabled. External arbitration is required.
The on-chip PCI arbiter is enabled (default).
(Binary)
Value
Debug information from the local bus controller (LBC) is driven on the
MSRCID and MDVAL signals
Debug information from the DDR SDRAM controller is driven on the
MSRCID and MDVAL signals (default).
0
1
Table
Section 19.4.1.3, “POR I/O Impedance Status and Control
Table
Table
25-Ω I/O drivers are used on the PCI interface.
42-Ω I/O drivers are used on the PCI interface (default).
4-27, enables a DDR memory controller debug mode
4-25, enable the on-chip PCI arbiter. Note that the
Table 4-24
4-26, selects which debug outputs (DDR or LBC
select the impedance of the PCI I/O
Meaning
Meaning
Meaning
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