MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 267

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

6.15.3
Freescale Semiconductor
Reset
38–40
41–47 EVENT Event selector. Up to 128 events selectable. These events are described in the PowerPC™ e500 Core Family
48–63
32–52
53–55
56–57
58–63
Bits
Bits
37
W
R
PMLCb0 (PMR272)
PMLCb1 (PMR273)
PMLCb2 (PMR274)
PMLCb3 (PMR275)
32
Figure 6-60. Local Control B Registers (PMLCb0–PMLCb3)/User Local Control B Registers
Name
THRESHMUL
THRESHOLD
CE
—
—
Name
Local Control B Registers (PMLCb0–PMLCb3,
UPMLCb0–UPMLCb3)
—
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Condition enable
0 PMC x overflow conditions cannot occur (PMC x cannot cause interrupts, cannot freeze counters)
1 Overflow conditions occur when the most-significant bit of PMC x is equal to 1.
It is recommended that CE be cleared when counter PMC x is selected for chaining.
Reserved, should be cleared.
Reference Manual.
Reserved, should be cleared.
Table 6-44. PMLCa0–PMLCa3 Field Descriptions (continued)
Reserved, should be cleared.
Threshold multiple
000 Threshold field is multiplied by 1 (PMLCb n [THRESHOLD] × 1)
001 Threshold field is multiplied by 2 (PMLCb n [THRESHOLD] × 2)
010 Threshold field is multiplied by 4 (PMLCb n [THRESHOLD] × 4)
011 Threshold field is multiplied by 8 (PMLCb n [THRESHOLD] × 8)
100 Threshold field is multiplied by 16 (PMLCb n [THRESHOLD] × 16)
101 Threshold field is multiplied by 32 (PMLCb n [THRESHOLD] × 32)
110 Threshold field is multiplied by 64 (PMLCb n [THRESHOLD] × 64)
111 Threshold field is multiplied by 128 (PMLCb n [THRESHOLD] × 128)
Reserved, should be cleared.
Threshold. Only events that exceed the threshold value are counted. Such events are
implementation-dependent as are the dimension (for example duration in cycles) and granularity
with which the value is interpreted.
By varying the value, software can obtain a profile of the event characteristics subject to
thresholding. For example, if PMC1 is configured to count cache misses that last longer than the
threshold value, software can obtain the distribution of cache miss durations for a given program by
monitoring the program repeatedly using a different threshold each time.
UPMLCb0 (PMR256)
UPMLCb1 (PMR257)
UPMLCb2 (PMR258)
UPMLCb3 (PMR259)
Table 6-45. PMLCb0–PMLCb3 Field Descriptions
—
(UPMLCb0–UPMLCb3)
All zeros
Description
Description
Access: PMLCb0–PMLCb3: Supervisor read/write
UPMLCb0–UPMLCb3: Supervisor/user read only
52
53
THRESHMUL
55
56 57 58
—
Core Register Summary
THRESHOLD
6-51
63