MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 476

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

I
11.5.7.1
In the slave transmitter routine, the received acknowledge bit (I2CSR[RXAK]) must be tested before
sending the next byte of data. The master signals an end-of-data by not acknowledging the data transfer
from the slave. When no acknowledge is received (I2CSR[RXAK] is set), the slave transmitter interrupt
routine must clear I2CCR[MTX] to switch the slave from transmitter to receiver mode. A dummy read of
I2CDR then releases SCL so that the master can generate a STOP condition. See
Service Routine Flowchart.”
11.5.7.2
When a master loses arbitration the following conditions all occur:
Thus, the slave interrupt service routine should first test I2CSR[MAL] and software should clear it if it is
set. See
11.5.8
Figure 11-11
flowchart may result in unpredictable I
the interrupt service routine may need to set I2CCR[TXAK] when the next-to-last byte is to be accepted.
It is recommended that an msync instruction follow each I
instruction execution.
11-24
2
C Interfaces
•
•
•
I2CSR[MAL] is set
I2CCR[MSTA] is cleared (changing the master to slave mode)
An interrupt occurs (if enabled) at the falling edge of the 9th clock of this transfer
Section 11.4.2.1, “Arbitration Control,”
shows an example algorithm for an I
Interrupt Service Routine Flowchart
Slave Transmitter and Received Acknowledge
Loss of Arbitration and Forcing of Slave Mode
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
2
C bus behavior. However, in the slave receive mode (not shown),
for more information.
2
C interrupt service routine. Deviation from the
2
C register read or write to guarantee in-order
Section 11.5.8, “Interrupt
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