MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 801

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

15.5.3.5.4
The HAFDUP register is written by the user.
Table 15-42
Freescale Semiconductor
Offset eTSEC1:0x2_450C; eTSEC3:0x2_650C
Reset
Reset
16–19
20–21
22–31
8–11
Bits
0–7
12
13
14
15
W
W
R
R
Retransmission Maximum
16
0
0
1
Collision Window This is a programmable field representing the slot time or collision window during which collisions
Retransmission
Alternate BEB
Excess Defer
No BackOff
Truncation
Maximum
BackOff
Alt BEB
describes the fields of the HAFDUP register.
BP No
Name
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
—
—
Half-Duplex Register (HAFDUP)
0
1
0
1
Reserved
This field is used while ALTERNATE BINARY EXPONENTIAL BACKOFF ENABLE is set. The
value programmed is substituted for the Ethernet standard value of ten. Its default is 0xA.
Alternate binary exponential backoff. This bit is cleared by default.
0 The Tx MAC follows the standard binary exponential back off rule.
1 The Tx MAC uses the ALTERNATE BINARY EXPONENTIAL BACKOFF TRUNCATION setting
Back pressure no backoff. This bit is cleared by default.
0 The Tx MAC follows the binary exponential back off rule.
1 The Tx MAC immediately re-transmits, following a collision, during back pressure operation.
No backoff. This bit is cleared by default.
0 The Tx MAC follows the binary exponential back off rule.
1 The Tx MAC immediately re-transmits following a collision.
Excessively deferred. This bit is set by default.
0 The Tx MAC aborts the transmission of a packet that is excessively deferred.
1 The Tx MAC allows the transmission of a packet that is excessively deferred.
This is a programmable field specifying the number of retransmission attempts following a collision
before aborting the packet due to excessive collisions. The standard specifies the attempt limit to
be 0xF (15d). Its default value is 0xF.
Reserved
occur in properly configured networks. Because the collision window starts at the beginning of
transmission, the preamble and SFD are included. Its default of 0x37 (55d) corresponds to the
count of frame bytes at the end of the window.
—
instead of the 802.3 standard tenth collision. The standard specifies that any collision after the
tenth uses one less than 210 as the maximum backoff time.
19
0
1
Figure 15-39. Half-Duplex Register Definition
20
Table 15-42. HAFDUP Field Descriptions
0
0
—
21
0
0
22
0
0
Figure 15-39
0
0
7
Alternate BEB
1
0
8
Truncation
0
0
1
1
describes the HAFDUP register.
11
0
1
Description
Alt BEB BP No BackOff No BackOff Excess Defer
12
0
0
Collision Window
Enhanced Three-Speed Ethernet Controllers
13
0
1
14
0
1
Access: Read/Write
15
31
1
1
15-71