MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 523

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

SW_RESET, or module initialization, which performs proper initialization of the S-box. To determine
when this is complete, poll the RESET_DONE bit in the AFEU status register.
Table 12-22
12.4.3.6
This status register, shown in
signals.
The AFEU status register is read-only. Writing to this location results in an address error being reflected
in the AFEU interrupt status register.
Freescale Semiconductor
Address AFEU 0x3_8018
0–60
Address AFEU 0x3_8028
Bits Name
61
62
63
Reset
Reset
W
W
R
R
SR
MI
—
RI
0
0
describes AFEU reset control register fields.
Reserved
Reset interrupt. Writing this bit active high causes AFEU interrupts signaling DONE and ERROR to be reset. It
further resets the state of the AFEU interrupt status register.
0 Do not reset
1 Reset interrupt logic
Module initialization is nearly the same as software reset, except that the interrupt control register remains
unchanged.
0 Do not reset
1 Reset most of AFEU
Software reset is functionally equivalent to hardware reset (the RESET signal), but only for AFEU. All registers
and internal states are returned to their defined reset state. On negation of SW_RESET, the AFEU enters a
routine to perform proper initialization of the S-box.
0 Do not reset
1 Full AFEU reset
AFEU Status Register (AFEUSR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 12-22. AFEU Reset Control Register Field Descriptions
—
Figure
Figure 12-24. AFEU Reset Control Register
Figure 12-25. AFEU Status Register
12-25, contains 6 bits that reflect the state of the AFEU internal
39 40
—
All zeros
All zeros
Description
OFL
47 48
IFL
55 56 57
—
Security Engine (SEC) 2.1
HALT
58
Access: Read/Write
Access: Read-only
59 60 61 62
—
60 61
RI MI SR
IE ID RD
62
12-45
63
63